CY7C1021BV33 Datasheet, PDF(1/11 Page) Cypress Semiconductor

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CY7C1021BV33 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 64K x 16 Static RAM

021B V33

CY7C1021BV33

Features

â¢ 3.3V operation (3.0Vâ3.6V)

â¢ High speed

â tAA = 10/12/15 ns

â¢ CMOS for optimum speed/power

â¢ Low Active Power (L version)

â 576 mW (max.)

â¢ Low CMOS Standby Power (L version)

â 1.80 mW (max.)

â¢ Automatic power-down when deselected

â¢ Independent control of upper and lower bits

â¢ Available in 44-pin TSOP II and 400-mil SOJ

â¢ Available in a 48-Ball Mini BGA package

Functional Description[1]

The CY7C1021BV is a high-performance CMOS static RAM

organized as 65,536 words by 16 bits. This device has an au-

tomatic power-down feature that significantly reduces power

consumption when deselected.

Logic Block Diagram

DATA IN DRIVERS

64K x 16

RAM Array

512 X 2048

COLUMN DECODER

64K x 16 Static RAM

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is

written into the location specified on the address pins (A0

through A15). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O9 through I/O16) is written into the location

specified on the address pins (A0 through A15).

Reading from the device is accomplished by taking Chip En-

able (CE) and Output Enable (OE) LOW while forcing the Write

Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then

data from the memory location specified by the address pins

will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW,

then data from memory will appear on I/O9 to I/O16. See the

truth table at the back of this data sheet for a complete descrip-

tion of read and write modes.

The input/output pins (I/O1 through I/O16) are placed in a

high-impedance state when the device is deselected

(CE HIGH), the outputs are disabled (OE HIGH), the BHE and

BLE are disabled (BHE, BLE HIGH), or during a write opera-

tion (CE LOW, and WE LOW).

The CY7C1021BV is available in 400-mil-wide SOJ, standard

44-pin TSOP Type II, and 48-ball mini BGA packages.

I/O1âI/O8

I/O9âI/O16

BHE

BLE

Pin Configurations

SOJ / TSOP II

Top View

A4 1

A3 2

A2 3

A1 4

A0 5

CE 6

I/O1 7

I/O2 8

I/O3 9

I/O4 10

VCC 11

VSS 12

I/O5 13

I/O6 14

I/O7 15

I/O8 16

WE 17

A15 18

A14 19

A13 20

A12 21

NC 22

44 A5

43 A6

42 A7

41 OE

40 BHE

39 BLE

38 I/O16

37 I/O15

36 I/O14

35 I/O13

34 VSS

33 VCC

32 I/O12

31 I/O11

30 I/O10

29 I/O9

28 NC

27 A8

26 A9

25 A10

24 A11

23 NC

Selection Guide

7C1021BV-8 7C1021BV-10 7C1021BV-12 7C1021BV-15

Maximum Access Time (ns)

Maximum Operating Current (mA) Commercial

170

160

150

140

Industrial

190

180

170

160

Maximum CMOS Standby Current Commercial

(mA)

0.500

Shaded areas contain advance information.

Note:

1. For guidelines on SRAM system design, please refer to the âSystem Design Guidelinesâ Cypress application note, available on the internet at www.cypress.com.

Cypress Semiconductor Corporation â¢ 3901 North First Street â¢ San Jose â¢ CA 95134 â¢ 408-943-2600

Document #: 38-05148 Rev. *A

Revised September 13, 2002

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