CY7C1021BN_11 Datasheet, PDF (1/14 Pages) Cypress Semiconductor – 1-Mbit (64 K × 16) Static RAM

CY7C1021BN, CY7C10211BN
1-Mbit (64 K × 16) Static RAM
1-Mbit (64 K × 16) Static RAM
Features
■ Temperature ranges
❐ Commercial: 0 °C to 70 °C
❐ Industrial: –40 °C to 85 °C
❐ Automotive-A: –40 °C to 85 °C
❐ Automotive-E: –40 °C to 125 °C
■ High speed
❐ t_AA = 15 ns (Automotive)
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed/power
■ Low active power
❐ 825 mW (maximum)
■ Automatic power down when deselected
■ Independent control of upper and lower bits
■ Available in Pb-free and non Pb-free 44-pin TSOP II and 44-pin
400-mil-wide SOJ
Functional Description
The CY7C1021BN/CY7C10211BN is a high performance CMOS
static RAM organized as 65,536 words by 16 bits. This device
has an automatic power down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is
LOW, then data from the input/output (I/O) pins (I/O₁ through
I/O₈), is written into the location specified on the address pins (A₀
through A₁₅). If Byte High Enable (BHE) is LOW, then data from
I/O pins (I/O₉ through I/O₁₆) is written into the location specified
on the address pins (A₀ through A₁₅).
Reading from the device is accomplished by taking CE and
Output Enable (OE) LOW while forcing WE HIGH. If BLE is LOW,
then data from the memory location specified by the address pins
appears on I/O₁ to I/O₈. If BHE is LOW, then data from memory
appears on I/O₉ to I/O₁₆. See the Truth Table on page 9 for a
complete description of read and write modes.
The I/O pins (I/O₁ through I/O₁₆) are placed in a high impedance
state when the device is deselected (CE HIGH), the outputs are
disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE
HIGH), or during a write operation (CE LOW, WE LOW).
The CY7C1021BN/CY7C10211BN is available in standard
44-pin TSOP type II and 44-pin 400-mil-wide SOJ packages.
Use part number CY7C1021BN when ordering 15 ns t_AA.
Logic Block Diagram
Data In Drivers
A₇
A₆
A₅
64K x 16
A₄
RAM Array
A₃
512 X 2048
A₂
A₁
A₀
Column Decoder
I/O₁–I/O₈
I/O₉–I/O₁₆
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-06494 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 26, 2011
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