CY7C1021BNV33_11 Datasheet, PDF (1/17 Pages) Cypress Semiconductor – 64 K × 16 Static RAM CMOS for optimum speed/power

64 K × 16 Static RAM
Features
■ 3.3 V operation (3.0 V–3.6 V)
■ High speed
❐ t_AA = 15 ns
■ CMOS for optimum speed/power
■ Low Active Power
❐ 576 mW (max)
■ Low CMOS Standby Power
❐ 1.80 mW (max)
■ Automatic power-down when deselected
■ Independent control of upper and lower bits
■ Available in 44-pin TSOP II and 400-mil SOJ
■ Available in a 48-ball Mini BGA package
CY7C1021BNV33
64 K × 16 Static RAM
Functional Description^[1]
The CY7C1021BNV33 is a high-performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
automatic power-down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is
LOW, then data from I/O pins (I/O₀ through I/O₇), is written into
the location specified on the address pins (A₀ through A₁₅). If
Byte High Enable (BHE) is LOW, then data from I/O pins (I/O₈
through I/O₁₅) is written into the location specified on the address
pins (A₀ through A₁₅).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins will
appear on I/O₀ to I/O₇. If Byte High Enable (BHE) is LOW, then
data from memory will appear on I/O₈ to I/O₁₅. See the truth table
at the back of this data sheet for a complete description of read
and write modes.
The input/output pins (I/O₀ through I/O₁₅) are placed in a
high-impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE LOW,
and WE LOW).
The CY7C1021BNV33 is available in 400-mil-wide SOJ,
standard 44-pin TSOP Type II, and 48-ball mini BGA packages.
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-06433 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 8, 2011
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