CY7C1021BNV33_09 Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 64K x 16 Static RAM

CY7C1021BNV33
Features
64K x 16 Static RAM
Functional Description^[1]
• 3.3V operation (3.0V–3.6V)
• High speed
— t_AA = 10, 12, 15 ns
• CMOS for optimum speed/power
• Low Active Power (L version)
— 576 mW (max.)
• Low CMOS Standby Power (L version)
— 1.80 mW (max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in 44-pin TSOP II and 400-mil SOJ
• Available in a 48-Ball Mini BGA package
The CY7C1021BNV is a high-performance CMOS static RAM
organized as 65,536 words by 16 bits. This device has an
automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O₁ through I/O₈), is
written into the location specified on the address pins (A₀
through A₁₅). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O₉ through I/O₁₆) is written into the location
specified on the address pins (A₀ through A₁₅).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O₁ to I/O₈. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O₉ to I/O₁₆. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O₁ through I/O₁₆) are placed in a
high-impedance state when the device is deselected
(CE HIGH), the outputs are disabled (OE HIGH), the BHE and
BLE are disabled (BHE, BLE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1021BNV is available in 400-mil-wide SOJ,
standard 44-pin TSOP Type II, and 48-ball mini BGA
packages.
Logic Block Diagram
DATA IN DRIVERS
Pin Configurations
SOJ / TSOP II
Top View
A₇
A₆
A₅
64K x 16
A₄
RAM Array
A₃
512 X 2048
A₂
A₁
A₀
COLUMN DECODER
I/O₁–I/O₈
I/O₉–I/O₁₆
BHE
WE
CE
OE
BLE
A₄ 1
A3 2
A2 3
A1 4
A0 5
CE ⁶
I/O1 7
I/O2 8
I/O3 9
I/O4 10
V_CC 11
V_SS 12
I/O5 13
I/O6 14
I/O7 15
I/O8 16
WE 17
A15 ¹⁸
A14 19
A13 20
A12 21
NC 22
44 _A5
43 A6
42 _A7
41 OE
40 _BHE
39 _BLE
38 _I/O16
37 _I/O15
36 _I/O14
35 _I/O13
34 _VSS
33 _VCC
32 I/O12
31 I/O11
30 I/O10
29 I/O9
28 _NC
27 A8
26 A9
25 A10
24 A11
23 NC
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-06433 Rev. **
Revised February 1, 2006