CY7C1021 Datasheet, PDF(1/9 Page) Cypress Semiconductor

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CY7C1021 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 64K x 16 Static RAM

021

CY7C1021

Features

â¢ High speed

â tAA = 12 ns

â¢ CMOS for optimum speed/power

â¢ Low active power

â 1320 mW (max.)

â¢ Automatic power-down when deselected

â¢ Independent Control of Upper and Lower bits

â¢ Available in 44-pin TSOP II and 400-mil SOJ

Functional Description

The CY7C1021 is a high-performance CMOS static RAM or-

ganized as 65,536 words by 16 bits. This device has an auto-

matic power-down feature that significantly reduces power

consumption when deselected.

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

64K x 16 Static RAM

(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is

written into the location specified on the address pins (A0

through A15). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O9 through I/O16) is written into the location

specified on the address pins (A0 through A15).

Reading from the device is accomplished by taking Chip En-

able (CE) and Output Enable (OE) LOW while forcing the write

enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then

data from the memory location specified by the address pins

will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW,

then data from memory will appear on I/O9 to I/O16. See the

truth table at the back of this data sheet for a complete descrip-

tion of read and write modes.

The input/output pins (I/O1 through I/O16) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), the BHE and BLE

are disabled (BHE, BLE HIGH), or during a write operation (CE

LOW, and WE LOW).

The CY7C1021 is available in standard 44-pin TSOP Type II

and 400-mil-wide SOJ packages.

Logic Block Diagram

DATA IN DRIVERS

64K x 16

RAM Array

512 X 2048

COLUMN DECODER

I/O1 â I/O8

I/O9 â I/O16

BHE

BLE

Pin Configuration

SOJ / TSOP II

Top View

A4 1

A3 2

A2 3

A1 4

A0 5

CE 6

I/O1 7

I/O2 8

I/O3 9

I/O4 10

VCC 11

VSS 12

I/O5 13

I/O6 14

I/O7 15

I/O8 16

WE 17

A15 18

A14 19

A13 20

A12 21

NC 22

44 A5

43 A6

42 A7

41 OE

40 BHE

39 BLE

38 I/O16

37 I/O15

36 I/O14

35 I/O13

34 VSS

33 VCC

32 I/O12

31 I/O11

30 I/O10

29 I/O9

28 NC

27 A8

26 A9

25 A10

24 A11

23 NC

1021-2

Selection Guide

Maximum Access Time (ns)

Maximum Operating Current (mA)

Maximum CMOS Standby Current (mA)

Shaded areas contain preliminary information.

Commercial

7C1021-10

220

0.5

7C1021-12

220

0.5

7C1021-15

220

0.5

7C1021-20

220

0.5

Cypress Semiconductor Corporation â¢ 3901 North First Street â¢ San Jose â¢ CA 95134 â¢ 408-943-2600

Document #: 38-05054 Rev. **

Revised August 24, 2001

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