CY7C1020V Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 32K x 16 Static RAM

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CY7C1020V
Features
• 3.3V operation (3.0V - 3.6V)
• High speed
— t_AA = 10 ns
• Low active power
— 540 mW (max., 12 ns)
• Very Low standby power
— 330 µW (max., “L” version)
• Automatic power-down when deselected
• Independent Control of Upper and Lower bytes
• Available in 44-pin TSOP II and 400-mil SOJ
Functional Description
The CY7C1020V is a high-performance CMOS static RAM or-
ganized as 32,768 words by 16 bits. This device has an auto-
matic power-down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking chip enable
(CE) and write enable (WE) inputs LOW. If byte low enable
32K x 16 Static RAM
(BLE) is LOW, then data from I/O pins (I/O₁ through I/O₈), is
written into the location specified on the address pins (A₀
through A₁₄). If byte high enable (BHE) is LOW, then data from
I/O pins (I/O₉ through I/O₁₆) is written into the location speci-
fied on the address pins (A₀ through A₁₄).
Reading from the device is accomplished by taking chip en-
able (CE) and output enable (OE) LOW while forcing the write
enable (WE) HIGH. If byte low enable (BLE) is LOW, then data
from the memory location specified by the address pins will
appear on I/O₁ to I/O₈. If byte high enable (BHE) is LOW, then
data from memory will appear on I/O₉ to I/O₁₆. See the truth
table at the back of this datasheet for a complete description
of read and write modes.
The input/output pins (I/O₁ through I/O₁₆) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020V is available in standard 44-pin TSOP type II
and 400-mil-wide SOJ packages.
Logic Block Diagram
DATA IN DRIVERS
A₆
A₅
A₄
32K x 16
A₃
RAM Array
A₂
A₁
A₀
COLUMN DECODER
Selection Guide
7C1020V-10
Maximum Access Time (ns)
10
Maximum Operating Current (mA)
130
L
100
Maximum CMOS Standby Current (mA)
1
L
0.1
I/O₁ – I/O₈
I/O₉ – I/O₁₆
BHE
WE
CE
OE
BLE ^1020V-1
Pin Configuration
SOJ / TSOP II
Top View
NC 1
A 14 2
A 13 3
A 12 4
A 11 ₅
CE 6
I/O_{1 7}
I/O₂ 8
I/O₃ 9
I/O₄ 10
V_CC 11
V_SS 12
I/O₅ 13
I/O_{6 14}
I/O_{7 15}
I/O₈ 16
WE 17
A 10 18
A₉ 19
A₈ 20
A₇ 21
NC 22
44 _A0
43 A₁
42 _A2
41 OE
40 _BHE
39 _BLE
38 _I/O16
37 _I/O15
36 _I/O14
35 _I/O13
34 V_SS
33 _VCC
32 I/O₁₂
31 I/O₁₁
30 I/O₁₀
29 I/O₉
28 _NC
27 A₃
26 A₄
25 A₅
24 ^A6
23 _NC
1020V-2
7C1020V-12
12
120
90
1
0.1
7C1020V-15
15
110
80
1
0.1
7C1020V-20
20
100
70
1
0.1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
October 1996 – Revised April 13, 1998