CY7C1020D_11 Datasheet, PDF (1/15 Pages) Cypress Semiconductor – 512K (32K x 16) Static RAM Automatic power-down when deselected

CY7C1020D
512K (32K x 16) Static RAM
Features
■ Pin- and function-compatible with CY7C1020B
■ High speed
— t_AA = 10 ns
■ Low active power
— I_CC = 80 mA @ 10ns
■ Low complementary metal oxide semiconductor (CMOS)
standby power
— I_SB2 = 3 mA
■ 2.0 V data retention
■ Automatic power-down when deselected
■ CMOS for optimum speed/power
■ Independent control of upper and lower bits
■ Available in Pb-free 44-pin 400-Mil wide Molded SOJ and
44-pin thin small outline package (TSOP) II packages
Logic Block Diagram
DATA IN DRIVERS
Functional Description ^[1]
The CY7C1020D is a high-performance CMOS static RAM
organized as 32,768 words by 16 bits. This device has an
automatic power-down feature that significantly reduces power
consumption when deselected.The input and output pins
(IO₀ through IO₁₅) are placed in a high-impedance state when:
■ Deselected (CE HIGH)
■ Outputs are disabled (OE HIGH)
■ BHE and BLE are disabled (BHE, BLE HIGH)
■ When the write operation is active (CE LOW, and WE LOW)
Write to the device by taking Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from IO pins (IO₀ through IO₇), is written into the location
specified on the address pins (A₀ through A₁₄). If Byte High
Enable (BHE) is LOW, then data from IO pins (IO₈ through IO₁₅)
is written into the location specified on the address pins (A₀
through A₁₄).
Reading from the device by taking Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appears on IO₀ to IO₇. If
Byte High Enable (BHE) is LOW, then data from memory
appears on IO₈ to IO₁₅. See the “Truth Table” on page 9 for a
complete description of read and write modes.
A₇
A₆
A₅
A₄
A₃
32K x 16
RAM Array
A₂
A₁
A₀
COLUMN DECODER
IO₀–IO₇
IO₈–IO₁₅
BHE
WE
CE
OE
BLE
Note
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-05463 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 7, 2011
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