CY7C1020DV33 Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 512K (32K x 16) Static RAM

CY7C1020DV33
512K (32K x 16) Static RAM
Features
• Pin-and function-compatible with CY7C1020CV33
• High speed
— t_AA = 10 ns
• Low active power
— I_CC = 60 mA @ 10 ns
• Low CMOS standby power
— I_SB2 = 3 mA
• 2.0V Data retention
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Independent control of upper and lower bits
• Available in Pb-free 44-pin 400-Mil wide Molded SOJ and
44-pin TSOP II packages
Functional Description^[1]
The CY7C1020DV33 is a high-performance CMOS static
RAM organized as 32,768 words by 16 bits. This device has
an automatic power-down feature that significantly reduces
power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O₀ through I/O₇), is
written into the location specified on the address pins (A₀
through A₁₄). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O₈ through I/O₁₅) is written into the location
specified on the address pins (A₀ through A₁₄).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O₀ to I/O₇. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O₈ to I/O₁₅. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
The input/output pins (I/O₀ through I/O₁₅) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020DV33 is available in Pb-free 44-pin 400-Mil
wide Molded SOJ and 44-pin TSOP II packages.
Logic Block Diagram
DATA IN DRIVERS
A₇
A₆
A₅
A₄
32K x 16
A₃
RAM Array
A₂
A₁
A₀
COLUMN DECODER
I/O₀–I/O₇
I/O₈–I/O₁₅
BHE
WE
CE
OE
BLE
Pin Configuration^[2]
SOJ/TSOP II
Top View
NC 1
44
A₃ 2
43
A₂ 3
42
A₁ 4
41
A₀ 5
40
CE 6
39
I/O₀ 7
38
I/O₁ 8
37
I/O₂ 9
36
I/O₃ 10
35
V_CC 11
34
V_{SS 12}
33
I/O_{4 13}
32
I/O_{5 14}
31
I/O_{6 15}
30
I/O_{7 16}
29
WE 17
28
A₄ 18
27
A_{14 19}
26
A_{13 20}
25
A_{12 21}
24
NC 22
23
A₅
A₆
A₇
OE
BHE
BLE
I/O₁₅
I/O₁₄
I/O₁₃
I/O₁₂
V_SS
V_CC
I/O₁₁
I/O₁₀
I/O₉
I/O₈
NC
A₈
A₉
A₁₀
A₁₁
NC
Notes
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com
2. NC pins are not connected on the die.
Cypress Semiconductor Corporation
Document #: 38-05461 Rev. *D
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised November 8, 2006
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