CY7C1020CV33_10 Datasheet, PDF (1/13 Pages) Cypress Semiconductor – 512 K (32 K × 16) Static RAM

CY7C1020CV33
512 K (32 K × 16) Static RAM
512 K (32 K × 16) Static RAM
Features
■ Pin- and function-compatible with CY7C1020CV33
■ Temperature Ranges
❐ Commercial: 0 °C to 70 °C
❐ Industrial: –40 °C to 85 °C
❐ Automotive: –40 °C to 125 °C
■ High speed
❐ t_AA = 10 ns
■ CMOS for optimum speed/power
■ Low active power
❐ 325 mW (max)
■ Automatic power-down when deselected
■ Independent control of upper and lower bits
■ Available in Pb-free and non Pb-free 44-pin TSOP II package
Logic Block Diagram
DATA IN DRIVERS
Functional Description
The CY7C1020CV33 is a high-performance CMOS static RAM
organized as 32,768 words by 16 bits. This device has an
automatic power-down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is
LOW, then data from I/O pins (I/O₁ through I/O₈), is written into
the location specified on the address pins (A₀ through A₁₄). If
Byte High Enable (BHE) is LOW, then data from I/O pins (I/O₉
through I/O₁₆) is written into the location specified on the address
pins (A₀ through A₁₄).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins will
appear on I/O₁ to I/O₈. If Byte High Enable (BHE) is LOW, then
data from memory will appear on I/O₉ to I/O₁₆. See the truth table
at the back of this data sheet for a complete description of read
and write modes.
The input/output pins (I/O₁ through I/O₁₆) are placed in a
high-impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE LOW,
and WE LOW).
The CY7C1020CV33 is available in standard 44-pin TSOP Type
II package.
A₇
A₆
A₅
32K × 16
A₄
RAM Array
A₃
A₂
A₁
A₀
COLUMN DECODER
I/O₁–I/O₈
I/O₉–I/O₁₆
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05133 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 2, 2010
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