CY7C1020CV26_10 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 512 Kb (32 K × 16) Static RAM

CY7C1020CV26
512 Kb (32 K × 16) Static RAM
Features
■ Temperature range
❐ Automotive: –40°C to 125°C
■ High speed
❐ t_AA = 15 ns
■ Optimized voltage range: 2.5V to 2.7V
■ Automatic power down when deselected
■ Independent control of upper and lower bits
■ CMOS for optimum speed and power
■ Package offered: 44-pin TSOP II
Functional Description
The CY7C1020CV26 is a high performance CMOS static RAM
organized as 32,768 words by 16 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O₁ through I/O₈), is
written into the location specified on the address pins (A₀
through A₁₄). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O₉ through I/O₁₆) is written into the location
specified on the address pins (A₀ through A₁₄).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins appears on I/O₁ to I/O₈. If Byte High Enable (BHE) is
LOW, then data from memory appears on I/O₉ to I/O₁₆. See
the Truth Table on page 7 for a complete description of read
and write modes.
The input/output pins (I/O₁ through I/O₁₆) are placed in a high
impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
The CY7C1020CV26 is available in a standard 44-pin TSOP
Type II.
Logic Block Diagram
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-05406 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 14, 2010
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