CY7C1018CV33 Datasheet, PDF (1/7 Pages) Cypress Semiconductor – 128K x 8 Static RAM

CY7C1018CV33
128K x 8 Static RAM
Features
• Pin- and function-compatible with CY7C1018BV33
• High speed
— t_AA = 8, 10, 12, 15 ns
• CMOS for optimum speed/power
• Center power/ground pinout
• Data retention at 2.0V
• Automatic power-down when deselected
• Easy memory expansion with CE and OE options
• Available in 300-mil-wide 32-pin SOJ
Functional Description^[1]
The CY7C1018CV33 is a high-performance CMOS static
RAM organized as 131,072 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers. This
Logic Block Diagram
device has an automatic power-down feature that significantly
reduces power consumption when deselected.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O₀ through I/O₇) is then written into the location
specified on the address pins (A₀ through A₁₆).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O₀ through I/O₇) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY7C1018CV33 is available in a standard 300-mil-wide
SOJ.
Pin Configurations
SOJ
Top View
A₀
A₁
A₂
A₃
A₄
A₅
A₆
A₇
A₈
CE
WE
INPUT BUFFER
512 x 256 x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
A_{0 1}
32 A₁₆
A_{1 2}
31 A₁₅
A_{2 3}
30 _A14
I/O₀
A_{3 4}
29 A₁₃
CE 5
28 _OE
I/O₁
I/O₀ 6
27 _I/O7
I/O₂
I/O₁ 7
V_{CC 8}
26 _I/O6
25 _VSS
I/O₃
V_{SS 9}
24 _VCC
I/O₂ 10
23 I/O₅
I/O₄
I/O_{3 11}
22 I/O₄
WE 12
21 ^A12
I/O₅
A_{4 13}
20 ^A11
A_{5 14}
19 ^A10
I/O₆
A_{6 15}
18 ^A9
A₇ 16
17 A₈
I/O₇
OE
Selection Guide
7C1018CV33-8
7C1018CV33-10 7C1018CV33-12 7C1018CV33-15 Unit
Maximum Access Time
8
10
12
15
ns
Maximum Operating Current
95
90
85
80
mA
Maximum Standby Current
5
5
5
5
mA
Note:
1. For guidelines on SRAM system designs, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05131 Rev. *C
Revised September 13, 2002