CY7C1012DV33 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 12-Mbit (512K X 24) Static RAM

PRELIMINARY
CY7C1012DV33
12-Mbit (512K X 24) Static RAM
Features
• High speed
— t_AA = 8 ns
• Low active power
— I_CC = 185 mA @ 8 ns
• Low CMOS standby power
— I_SB2 = 25 mA
• Operating voltages of 3.3 ± 0.3V
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Available in Lead Pb-Free Standard 119-ball PBGA
Functional Description
The CY7C1012DV33 is a high-performance CMOS static
RAM organized as 512K words by 24 bits. Each data byte is
separately controlled by the individual chip selects (CE₁, CE₂,
CE₃). CE₁ controls the data on the I/O₀–I/O₇, while CE₂
controls the data on I/O₈–I/O₁₅, and CE₃ controls the data on
the data pins I/O₁₆–I/O₂₃. This device has an automatic
Functional Block Diagram
INPUT BUFFER
power-down feature that significantly reduces power
consumption when deselected.
Writing the data bytes into the SRAM is accomplished when
the chip select controlling that byte is LOW and the write
enable input (WE) input is LOW. Data on the respective
input/output (I/O) pins is then written into the location specified
on the address pins (A₀–A₁₈). Asserting all of the chip selects
LOW and write enable LOW will write all 24 bits of data into
the SRAM. Output enable (OE) is ignored while in WRITE
mode.
Data bytes can also be individually read from the device.
Reading a byte is accomplished when the chip select
controlling that byte is LOW and write enable (WE) HIGH while
output enable (OE) remains LOW. Under these conditions, the
contents of the memory location specified on the address pins
will appear on the specified data input/output (I/O) pins.
Asserting all the chip selects LOW will read all 24 bits of data
from the SRAM.
The 24 I/O pins (I/O₀–I/O₂₃) are placed in a high-impedance
state when all the chip selects are HIGH or when the output
enable (OE) is HIGH during a READ mode. For further details,
refer to the truth table of this data sheet.
A₀
A₁
A₂
A₃
A₄
A₅
512K x 24
ARRAY
A₆
A₇
A₈
A₉
I/O₀–I/O₇
I/O₈–I/O₁₅
I/O₁₆–I/O₂₃
COLUMN
DECODER
CONTROL LOGIC
CE₁, CE₂, CE₃
WE
OE
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
–8
Unit
8
ns
185
mA
25
mA
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05610 Rev. *B
Revised September 4, 2006
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