CY7C1012AV33_11 Datasheet, PDF (1/13 Pages) Cypress Semiconductor – 512 K × 24 Static RAM TTL-compatible inputs and outputs

CY7C1012AV33
512 K × 24 Static RAM
512 K × 24 Static RAM
Features
■ High speed
❐ t_AA = 8 ns
■ Low active power
❐ 1080 mW (max)
■ Operating voltages of 3.3 ± 0.3 V
■ 2.0 V data retention
■ Automatic power-down when deselected
■ TTL-compatible inputs and outputs
■ Easy memory expansion with CE₀, CE₁ and CE₂ features
■ Available in non Pb-free 119 ball PBGA.
Functional Block Diagram
Functional Description
The CY7C1012AV33 is a high-performance CMOS static RAM
organized as 512 K words by 24 bits. Each data byte is
separately controlled by the individual chip selects (CE₀, CE₁,
CE₂). CE₀ controls the data on the I/O₀–I/O₇, while CE₁ controls
the data on I/O₈–I/O₁₅, and CE₂ controls the data on the data
pins I/O₁₆–I/O₂₃. This device has an automatic power-down
feature that significantly reduces power consumption when
deselected.
Writing the data bytes into the SRAM is accomplished when the
chip select controlling that byte is LOW and the write enable input
(WE) input is LOW. Data on the respective input/output (I/O) pins
is then written into the location specified on the address pins
(A₀–A₁₈). Asserting all of the chip selects LOW and write enable
LOW will write all 24 bits of data into the SRAM. Output enable
(OE) is ignored while in WRITE mode.
Data bytes can also be individually read from the device.
Reading a byte is accomplished when the chip select controlling
that byte is LOW and write enable (WE) HIGH while output
enable (OE) remains LOW. Under these conditions, the contents
of the memory location specified on the address pins will appear
on the specified data input/output (I/O) pins. Asserting all the chip
selects LOW will read all 24 bits of data from the SRAM.
The 24 I/O pins (I/O₀–I/O₂₃) are placed in a high-impedance
state when all the chip selects are HIGH or when the output
enable (OE) is HIGH during a READ mode. For further details,
refer to the truth table of this data sheet.
The CY7C1012AV33 is available in a standard 119-ball PBGA.
INPUT BUFFER
A₀
A₁
A₂
AA₃₄
A₅
512K x 24
ARRAY
A₆
AAA₉₇₈
I/O₀–I/O₇
I/O₈–I/O₁₅
I/O₁₆–I/O₂₃
COLUMN
DECODER
CONTROL LOGIC
CE₀, CE₁, CE₂
WE
OE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05254 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 7, 2011
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