CY7C1011DV33 Datasheet, PDF(1/11 Page) Cypress Semiconductor

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CY7C1011DV33 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 2-Mbit (128K x 16)Static RAM

CY7C1011DV33

2-Mbit (128K x 16)Static RAM

Features

Functional Description

â¢ Pin-and function-compatible with CY7C1011CV33

â¢ High speed

â tAA = 10 ns

â¢ Low active power

â ICC = 90 mA @ 10 ns (Industrial)

â¢ Low CMOS standby power

â ISB2 = 10 mA

â¢ Data Retention at 2.0 V

â¢ Automatic power-down when deselected

â¢ Independent control of upper and lower bits

â¢ Easy memory expansion with CE and OE features

â¢ Available in Lead-Free 44-pin TSOP II, and 48-ball VFBGA

The CY7C1011DV33 is a high-performance CMOS Static

RAM organized as 128K words by 16 bits.

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is

written into the location specified on the address pins (A0

through A16). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O8 through I/O15) is written into the location

specified on the address pins (A0 through A16).

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is

LOW, then data from memory will appear on I/O8 to I/O15. See

the truth table at the back of this data sheet for a complete

description of read and write modes.

The input/output pins (I/O0 through I/O15) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), the BHE and BLE

are disabled (BHE, BLE HIGH), or during a write operation (CE

LOW, and WE LOW).

The CY7C1011DV33 is available in standard Lead-Free

44-pin TSOP II with center power and ground pinout, as well

as 48-ball fine-pitch ball grid array (VFBGA) packages

Logic Block Diagram

INPUT BUFFER

128K X 16

COLUMN

DECODER

I/O0âI/O7

I/O8âI/O15

BHE

BLE

Pin Configuration

TSOP II

Top View

A4 1

A3 2

A2 3

A1 4

A0 5

CE 6

I/O0 7

I/O1 8

I/O2 9

I/O3 10

VCC 11

VSS 12

I/O4 13

I/O5 14

I/O6 15

I/O7 16

WE 17

A16 18

A15 19

A14 20

A13 21

A12 22

44 A5

43 A6

42 A7

41 OE

40 BHE

39 BLE

38 I/O15

37 I/O14

36 I/O13

35 I/O12

34 VSS

33 VCC

32 I/O11

31 I/O10

30 I/O9

29 I/O8

28 NC

27 A8

26 A9

25 A10

24 A11

23 NC

Note

1. For guidelines on SRAM system design, please refer to the âSystem Design Guidelinesâ Cypress application note, available on the internet at www.cypress.com

Cypress Semiconductor Corporation

Document #: 38-05609 Rev. *C

â¢ 198 Champion Court â¢ San Jose, CA 95134-1709 â¢ 408-943-2600

Revised July 14, 2006

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