CY7C1010DV33 Datasheet, PDF (1/7 Pages) Cypress Semiconductor – 2-Mbit (256K x 8)Static RAM

CY7C1010DV33
2-Mbit (256K x 8)Static RAM
Features
• Pin and function compatible with CY7C1010CV33
• High speed
— t_AA = 10 ns
• Low active power
— I_CC = 90 mA @ 10 ns
• Low CMOS standby power
— I_SB2 = 10 mA
• 2.0V data retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE features
• Available in Lead-Free 44-pin TSOP II package
Functional Description^[1]
The CY7C1010DV33 is a high-performance CMOS Static
RAM organized as 256K words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O₀ through I/O₇) is then written into the location
specified on the address pins (A₀ through A₁₇).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O₀ through I/O₇) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW, and WE LOW).
The CY7C1010DV33 is available in standard 44-pin TSOP II
package with center power and ground (revolutionary) pinout.
Logic Block Diagram
Pin Configuration
TSOP II
Top View
A₀
A₁
A₂
A₃
A₄
A₅
A₆
A₇
A₈
A₉
A₁₀
CE
WE
INPUT BUFFER
256K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O₀
I/O₁
I/O₂
I/O₃
I/O₄
I/O₅
I/O₆
I/O₇
NC 1
NC 2
A₄ 3
A₃ 4
A_{2 5}
A₁ 6
A_{0 7}
CE 8
I/O₀ 9
I/O₁ 10
V_CC 11
V_SS 12
I/O₂ 13
I/O_{3 14}
WE 15
A₁₇ 16
A₁₆ 17
A₁₅ ¹⁸
A₁₄ 19
A₁₃ 20
NC 21
NC 22
44 _NC
43 _NC
42 _NC
41 A₅
40 _A6
39 _A7
38 _A8
37 _OE
36 _I/O7
35 _I/O6
34 _VSS
33 _VCC
32 I/O₅
31 I/O₄
30 A₉
29 A₁₀
28 _A11
27 A₁₂
26 NC
25 NC
24 ^NC
23 NC
OE
Selection Guide
–10
Unit
Maximum Access Time
10
ns
Maximum Operating Current
90
mA
Maximum CMOS Standby Current
10
mA
Note:
1. For guidelines on SRAM system design, please refer to the System Design Guidelines Cypress application note, available on the internet at www.cypress.com
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 001-00062 Rev. *A
Revised April 17, 2006
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