CY7C1009V33 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – 128K x 8 Static RAM

CY7C1009V33
CY7C109V33
128K x 8 Static RAM
Features
• High speed
— t_AA = 15, 20, 25ns
• V_CC = 3.3V ± 10%
• Low active power
— 432 mW (max.)
— 288 mW (L version)
• Low CMOS standby power
— 18 mW (max.)
— 7.2 mW (L version)
• 2.0V Data Retention
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE₁, CE₂, and OE options
Functional Description
The CY7C109V33/CY7C1009V33 is a high-performance
CMOS static RAM organized as 131,072 words by 8 bits. Easy
memory expansion is provided by an active LOW Chip Enable
(CE₁), an active HIGH Chip Enable (CE₂), an active LOW Out-
put Enable (OE), and three-state drivers. Writing to the device
is accomplished by taking Chip Enable one (CE₁) and Write
Enable (WE) inputs LOW and Chip Enable two (CE₂) input
HIGH. Data on the eight I/O pins (I/O₀ through I/O₇) is then
written into the location specified on the address pins (A₀
through A₁₆).
Reading from the device is accomplished by taking Chip En-
able one (CE₁) and Output Enable (OE) LOW while forcing
Write Enable (WE) and Chip Enable two (CE₂) HIGH. Under
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
The eight input/output pins (I/O₀ through I/O₇) are placed in a
high-impedance state when the device is deselected (CE₁
HIGH or CE₂ LOW), the outputs are disabled (OE HIGH), or
during a write operation (CE₁ LOW, CE₂ HIGH, and WE LOW).
The CY7C109V33 is available in standard 32-pin,
400-mil-wide SOJ package. The CY7C1009V33 is available in
a 32-pin, 300-mil-wide SOJ package. The CY7C1009V33 and
CY7C109V33 are functionally equivalent in all other respects.
Logic Block Diagram
Pin Configurations
SOJ
Top View
INPUT BUFFER
A₀
A₁
A₂
A₃
A₄
A₅
A₆
512 x 256 x 8
ARRAY
A₇
A₈
CE₁
CE₂
COLUMN
DECODER
WE
OE
Selection Guide
POWER
DOWN
I/O₀
I/O₁
I/O₂
I/O₃
A₁₁
1
A₉
2
I/O₄
A₈
3
A₁₃
4
WE
5
CE₂
6
I/O₅
A₁₅
7
V_CC
8
NC 9
I/O₆
A₁₆
10
A₁₄
11
A₁₂
12
A₇
13
I/O₇
A₆
14
A₅
15
109V33–1
A₄
16
NC 1
A_{16 2}
A₁₄ 3
A₁₂ 4
A₇ 5
A₆ 6
A_{5 7}
A₄ 8
A₃ 9
A₂ 10
A_{1 11}
A₀ 12
I/O_{0 13}
I/O_{1 14}
I/O_{2 15}
GND ₁₆
32 VCC
31 A₁₅
30 CE₂
29 WE
28 _A13
27 _A8
26 _A9
25 _A11
24 _OE
23 A₁₀
22 CE₁
21 I/O7
20 ^I/O6
19 ^I/O5
18 ^I/O4
17 I/O3 _{109V33–2}
TSOP I
Top View
(not to scale)
32 OE
31 A₁₀
30 CE
29 I/O₇
28 I/O₆
27 I/O₅
26 I/O₄
25 I/O₃
24 GND
23 I/O₂
22 I/O₁
21 I/O₀
20 A₀
19 A₁
18 A₂
17 A₃
109V33–3
7C109V33-12 7C109V33-15 7C109V33-20 7C109V33-25
7C1009V33-12 7C1009V33-15 7C1009V33-20 7C1009V33-25
Maximum Access Time (ns)
12
15
20
20
Maximum Operating Current (mA)
130
120
110
110
Maximum Operating Current (mA) Low Power Version
90
80
70
70
Maximum CMOS Standby Current (mA) Standard
5
5
5
5
Maximum CMOS Standby Current (mA) Low Power Version
2
2
2
2
Shaded areas contain preliminary information.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
September 3, 1999