CY7C09569V_12 Datasheet, PDF (1/32 Pages) Cypress Semiconductor – 3.3 V 16 K / 32 K × 36 FLEx36® Synchronous Dual-Port Static RAM

CY7C09569V CY7C09579V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3 V 16 K / 32 K × 36 FLEx36®
Synchronous Dual-Port Static RAM
CY7C09569V
CY7C09579V
3.3 V 16 K / 32 K × 36 FLEx36^®
Synchronous Dual-Port Static RAM
Features
■ True dual-ported memory cells which allow simultaneous
access of the same memory location
■ Two flow-through/pipelined devices
❐ 16 K × 36 organization (CY7C09569V)
❐ 32 K × 36 organization (CY7C09579V)
■ 0.25-micron CMOS for optimum speed/power
■ Three modes
❐ Flow-through
❐ Pipelined
❐ Burst
■ Bus-matching capabilities on right port
(×36 to ×18 or ×9)
■ Byte-select capabilities on left port
■ 100-MHz pipelined operation
■ High-speed clock to data access 5/6 ns
■ 3.3 V low operating power
❐ Active = 250 mA (typical)
❐ Standby = 10 μA (typical)
■ Fully synchronous interface for ease of use
■ Burst counters increment addresses internally
❐ Shorten cycle times
❐ Minimize bus noise
❐ Supported in flow-through and pipelined modes
■ Counter address read back via I/O lines
■ Single chip enable
■ Automatic power-down
■ Commercial and industrial temperature ranges
■ Compact package
❐ 144-pin TQFP (20 × 20 × 1.4 mm)
❐ 144-pin Pb-free TQFP (20 × 20 × 1.4 mm)
❐ 172-ball BGA (1.0-mm pitch) (15 × 15 × 0.51 mm)
Functional Description
The CY7C09569V and CY7C09579V are high-speed 3.3 V
synchronous CMOS 16 K and 32 K × 36 dual-port static RAMs.
Two ports are provided, permitting independent, simultaneous
access for reads and writes to any location in memory.
Registers on control, address, and data lines allow for minimal
set-up and hold times. In pipelined output mode, data is regis-
tered for decreased cycle time. Clock to data valid t_CD2 = 5 ns
(pipelined). Flow-through mode can also be used to bypass
the pipelined output register to eliminate access latency. In
flow-through mode data will be available t_CD1 = 12.5 ns after
the address is clocked into the device. Pipelined output or
flow-through mode is selected via the FT/Pipe pin.
Each port contains a burst counter on the input address
register. The internal write pulse width is independent of the
external R/W LOW duration. The internal write pulse is
self-timed to allow the shortest possible cycle times.
A HIGH on CE for one clock cycle will power down the internal
circuitry to reduce the static power consumption. In the
pipelined mode, one cycle is required with CE LOW to
reactivate the outputs.
Counter Enable Inputs are provided to stall the operation of the
address input and utilize the internal address generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW-to-HIGH
transition of that port’s clock signal. This will read/write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array and will loop back to the start. Counter Reset (CNTRST)
is used to reset the burst counter.
Parts are available in 144-pin Thin Quad Plastic Flatpack
(TQFP), 144-pin Pb-free Thin Quad Plastic Flatpack (TQFP)
and 172-ball Ball Grid Array (BGA) packages.
Selection Guide
f_MAX2 (pipelined)
Maximum access time (clock to data, pipelined)
Typical operating current I_CC
Typical standby current for I_SB1 (both ports TTL level)
Typical standby current for I_SB3 (both ports CMOS level)
CY7C09569V
CY7C09579V
–100
–83
100
83
5
6
250
240
30
25
10
10
Unit
MHz
ns
mA
mA
μA
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-06054 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 23, 2011