CY7C09349AV_12 Datasheet, PDF (1/20 Pages) Cypress Semiconductor – 3.3 V 4 K/8 K × 18 Synchronous Dual Port Static RAM

CY7C09359AV3.3 V 4 K/8 K × 18
Synchronous Dual Port Static RAM
CY7C09349AV
CY7C09359AV
3.3 V 4 K/8 K × 18
Synchronous Dual Port Static RAM
3.3 V 4 K/8 K × 18 Synchronous Dual Port Static RAM
Features
■ True dual ported memory cells which allow simultaneous
access of the same memory location
■ Two flow-through/pipelined devices
❐ 4 K × 18 organization (CY7C09349AV)
❐ 8 K × 18 organization (CY7C09359AV)
■ Three modes
❐ Flow-through
❐ Pipelined
❐ Burst
■ Pipelined output mode on both ports allows fast 67-MHz
operation
■ 0.35-micron complementary metal oxide semiconductor
(CMOS) for optimum speed/power
Logic Block Diagram
R/W_L
UB_L
■ High-speed clock to data access 9 and 12 ns (max)
■ 3.3 V low operating power
❐ Active = 135 mA (typical)
❐ Standby = 10 µA (typical)
■ Fully synchronous interface for easier operation
■ Burst counters increment addresses internally
❐ Shorten cycle times
❐ Minimize bus noise
❐ Supported in flow-through and pipelined modes
■ Dual chip enables for easy depth expansion
■ Upper and lower byte controls for bus matching
■ Automatic power-down
■ Available in 100-pin thin quad flat pack (TQFP)
R/W_R
UB_R
CE_0L
1
CE_1L
0
LB_L
0/1
OE_L
1
CE_0R
0
CE_1R
0/1
LB_R
OE_R
FT/Pipe_L
I/O_9L–I/O_17L
I/O_0L–I/O_8L
[1]
A_0L–A_11/12L
CLK_L
ADS_L
CNTEN_L
CNTRST_L
1b 0b 1a 0a
0/1 b
a
9
9
12/13
Counter/
Address
Register
Decode
I/O
Control
I/O
Control
True Dual Ported
RAM Array
0a 1a 0b 1b
a
b 0/1
9
FT/Pipe_R
I/O_9R–I/O_17R
Counter/
Address
Register
Decode
9
12/13
I/O_0R–I/O_8R
[1]
A_0R–A_11/12R
CLK_R
ADS_R
CNTEN_R
CNTRST_R
Note
1. A₀–A₁₁ for 4 K; A₀–A₁₂ for 8 K devices.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-63888 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 28, 2011