CY7C09349A Datasheet, PDF (1/17 Pages) Cypress Semiconductor – 4K/8K x 18 Synchronous Dual-Port Static RAM

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CY7C09349A
CY7C09359A
4K/8K x 18
Synchronous Dual-Port Static RAM
Features
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
• Two Flow-Through/Pipelined devices
— 4K x 18 organization (CY7C09349A)
— 8K x 18 organization (CY7C09359A)
• Three Modes
— Flow-Through
— Pipelined
— Burst
• Pipelined output mode on both ports allows fast
100-MHz cycle time
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 6.5^[1]/7.5/9/12 ns
(max.)
• Low operating power
— Active = 200 mA (typical)
— Standby = 0.05 mA (typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Upper and lower byte controls for bus matching
• Automatic power-down
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP
v
Logic Block Diagram
R/W_L
UB_L
R/W_R
UB_R
CE_0L
1
CE_1L
0
LB_L
0/1
OE_L
1
CE_0R
0
CE_1R
0/1
LB_R
OE_R
FT/Pipe_L
I/O_9L–I/O_17L
I/O_0L–I/O_8L
[2]
A_0L–A_11/12L
CLK_L
ADS_L
CNTEN_L
CNTRST_L
1b 0b 1a 0a
0/1 b
a
9
9
12/13
Counter/
Address
Register
Decode
Notes:
1. See page 6 for Load Conditions.
2. A₀–A₁₁ for 4K; A₀–A₁₂ for 8K devices.
I/O
Control
I/O
Control
True Dual-Ported
RAM Array
0a 1a 0b 1b
a
b 0/1
9
FT/Pipe_R
I/O_9R–I/O_17R
Counter/
Address
Register
Decode
9
12/13
I/O_0R–I/O_8R
[2]
A_0R–A_11/12R
CLK_R
ADS_R
CNTEN_R
CNTRST_R
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06048 Rev. **
Revised September 19, 2001