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CY7C09159AV_05 Datasheet, PDF (1/16 Pages) Cypress Semiconductor – 3.3V 8K/16K x 9 Synchronous Dual Port Static RAM | |||
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CY7C09159AV
CY7C09169AV3.3V 8K/16K x 9
Synchronous Dual Port Static RAM
CY7C09159AV
CY7C09169AV
3.3V 8K/16K x 9
Synchronous Dual Port Static RAM
Features
⢠True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
⢠Two Flow-Through/Pipelined devices
â 8K x 9 organization (CY7C09159AV)
â 16K x 9 organization (CY7C09169AV)
⢠Three Modes
â Flow-Through
â Pipelined
â Burst
⢠Pipelined output mode on both ports allows fast 83-MHz
operation
⢠0.35-micron CMOS for optimum speed/power
⢠High-speed clock to data access 9 and 12 ns (max.)
⢠3.3V Low operating power
â Active = 135 mA (typical)
â Standby = 10 µA (typical)
⢠Fully synchronous interface for easier operation
⢠Burst counters increment addresses internally
â Shorten cycle times
â Minimize bus noise
â Supported in Flow-Through and Pipelined modes
⢠Dual Chip Enables for easy depth expansion
⢠Automatic power-down
⢠Commercial and industrial temperature ranges
⢠Available in 100-pin TQFP
⢠Pb-Free packages available
Logic Block Diagram
R/WL
OEL
R/WR
OER
CE0L
1
CE1L
0
0/1
1
CE0R
0
CE1R
0/1
FT/PipeL
I/O0LâI/O8L
1
0
0/1
9
A0âA[112]/13L
CLKL
ADSL
CNTENL
CNTRSTL
13/14
Counter/
Address
Register
Decode
Notes:
1. A0âA12 for 8K; A0âA13 for 16K.
I/O
Control
I/O
Control
True Dual-Ported
RAM Array
0
1
0/1
9
FT/PipeR
I/O0RâI/O8R
Counter/
Address
Register
Decode
13/14
A0â[1A]12/13R
CLKR
ADSR
CNTENR
CNTRSTR
Cypress Semiconductor Corporation ⢠198 Champion Court ⢠San Jose, CA 95134-1709 ⢠408-943-2600
Document #: 38-06053 Rev. *B
Revised September 6, 2005
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