CY7C09159AV Datasheet, PDF (1/17 Pages) Cypress Semiconductor – 3.3V 8K/16K x 9 Synchronous Dual Port Static RAM

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CY7C09159AV
CY7C09169AV
3.3V 8K/16K x 9
Synchronous Dual Port Static RAM
Features
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• Two Flow-Through/Pipelined devices
— 8K x 9 organization (CY7C09159AV)
— 16K x 9 organization (CY7C09169AV)
• Three Modes
— Flow-Through
— Pipelined
— Burst
• Pipelined output mode on both ports allows fast 83-MHz
operation
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 9 and 12 ns (max.)
• 3.3V Low operating power
— Active = 135 mA (typical)
— Standby = 10 µA (typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Automatic power-down
• Commercial and industrial temperature ranges
• Available in 100-pin TQFP
v
Logic Block Diagram
R/W_L
OE_L
R/W_R
OE_R
CE_0L
1
CE_1L
0
0/1
1
CE_0R
0
CE_1R
0/1
FT/Pipe_L
I/O_0L−I/O_8L
1
0
0/1
9
[1]
A₀−A_12/13L
CLK_L
ADS_L
CNTEN_L
CNTRST_L
13/14
Counter/
Address
Register
Decode
Notes:
1. A₀−A₁₂ for 8K; A₀−A₁₃ for 16K.
I/O
Control
I/O
Control
True Dual-Ported
RAM Array
0
1
0/1
9
FT/Pipe_R
I/O_0R−I/O_8R
Counter/
Address
Register
Decode
13/14
[1]
A₀−A_12/13R
CLK_R
ADS_R
CNTEN_R
CNTRST_R
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06053 Rev. **
Revised September 21, 2001