CY7C09079A Datasheet, PDF (1/18 Pages) Cypress Semiconductor – 32K x 8/9 Synchronous Dual-Port Static RAM

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CY7C09079A
CY7C09179A
Features
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
• Two Flow-Through/Pipelined devices
— 32K x 8/9 organizations (CY7C09079A/179A)
• Three Modes
— Flow-Through
— Pipelined
— Burst
• Pipelined output mode on both ports allows fast 100-
MHz cycle time
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 6.5^[1]/7.5/9/12 ns
(max.)
Logic Block Diagram
R/W_L
OE_L
32K x 8/9 Synchronous
Dual-Port Static RAM
• Low operating power
— Active = 195 mA (typical)
— Standby = 0.05 mA (typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
— Shorten cycle times
— Minimize bus noise
— Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Automatic power-down
• Commercial temperature range
• Available in 100-pin TQFP
• Pin-compatible and functionally equivalent to
IDT709079
R/W_R
OE_R
CE_0L
1
CE_1L
0
0/1
1
CE_0R
0
CE_1R
0/1
FT/Pipe_L
[2]
I/O_0L–I/O_7/8L
1
0
0/1
8/9
A₀–A_14L
CLK_L
ADS_L
CNTEN_L
CNTRST_L
15
Counter/
Address
Register
Decode
Notes:
1. See page 7 for Load Conditions.
2. I/O₀–I/O₇ for x8 devices; I/O₀–I/O₈ for x9 devices.
I/O
Control
I/O
Control
True Dual-Ported
RAM Array
0
1
0/1
8/9
FT/Pipe_R
[2]
I/O_0R–I/O_7/8R
15
Counter/
Address
Register
Decode
A₀–A_14R
CLK_R
ADS_R
CNTEN_R
CNTRST_R
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06049 Rev. *A
Revised December 27, 2002