CY7C056V_05 Datasheet, PDF (1/23 Pages) Cypress Semiconductor – 3.3V 16K/32K x 36 FLEx36™ Asynchronous Dual-Port Static

CY7C056V CY7C057V CY7C037V CY7C038V3.3V 16K/32K x 36
FLEx36™ Asynchronous Dual-Port Static RAM
CY7C056V
CY7C057V
3.3V 16K/32K x 36
FLEx36™ Asynchronous Dual-Port Static
Features
• True dual-ported memory cells that allow simultaneous
access of the same memory location
• 16K x 36 organization (CY7C056V)
• 32K x 36 organization (CY7C057V)
• 0.25-micron CMOS for optimum speed/power
• High-speed access: 12/15/20 ns
• Low operating power
— Active: I_CC = 250 mA (typical)
— Standby: I_SB3 = 10 µA (typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 72 bits or more using
Master/Slave Chip Select when using more than one
device
Logic Block Diagram
• On-Chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Byte Select on Left Port
• Bus Matching on Right Port
• Depth Expansion via dual chip enables
• Pin select for Master or Slave
• Commercial and Industrial Temperature Ranges
• Available in 144-Pin TQFP or 172-Ball BGA
• Pb-Free packages available
• Compact packages:
— 144-Pin TQFP (20 x 20 x 1.4 mm)
— 172-Ball BGA (1.0-mm pitch) (15 x 15 x.51 mm)
R/W_L
B₀–B₃
CE_0L
CE_1L
OE_L
I/O_0L–I/O_8L
I/O_9L–I/O_17L
I/O_18L–I/O_26L
I/O_27L–I/O_35L
Left
Port
CE_L
Control
Logic
9
9
9
9
I/O
Control
I/O
Control
Right
Port
Control
Logic
CE_R
9
9
Bus
9
Match
9
R/W_R
CE_0R
CE_1R
OE_R
BA
WA
9/18/36
I/O_R
BM
SIZE
A_0L–A_13/14^[_L^1]
14/15
Address
Decode
True Dual-Ported
RAM Array
Address
Decode
14/15
A_0R–A_13/14R^[1]
14/15
14/15
SEM_L
BUSY_L^[2]
INT_L
Notes:
1. A₀–A₁₃ for 16K; A₀–A₁₄ for 32K devices.
2. BUSY is an output in Master mode and an input in Slave mode.
Interrupt
Semaphore
Arbitration
M/S
SEM_R
BUSY_R^[2]
INT_R
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-06055 Rev. *B
Revised September 6, 2005