|
CY7C0430V Datasheet, PDF (1/36 Pages) Cypress Semiconductor – 3.3V 64K x 18 Synchronous QuadPort™ Static RAM | |||
|
30V
PRELIMINARY
CY7C0430V
3.3V 64K x 18
Synchronous QuadPort⢠Static RAM
Features
⢠True four-ported memory cells which allow simulta-
neous access of the same memory location
⢠Synchronous Pipelined device
â 64K x 18 organization
⢠Pipelined output mode allows fast 133-MHz operation
⢠High Bandwidth up to 10 Gbps (133 MHz x 18 bits wide
x 4 ports)
⢠0.25-micron CMOS for optimum speed/power
⢠High-speed clock to data access 4.7 ns (max.)
⢠3.3V Low operating power
â Active = 750mA (maximum)
â Standby = 1mA (maximum)
⢠Counter wrap-around control
â Internal mask register controls counter wrap-around
â Counter-Interrupt flags to indicate wrap-around
⢠Counter readback on address lines
⢠Mask register readback on address lines
⢠Interrupt flags for message passing
⢠Master reset for all ports
⢠Width and depth expansion capabilities
⢠Dual Chip Enables on all ports for easy depth expansion
⢠Separate upper-byte and lower-byte controls on all
ports
⢠272-BGA package (27 mm x 27 mm 1.27 mm ball pitch)
⢠Commercial and Industrial temperature ranges
⢠IEEE 1149.1 JTAG boundary scan
⢠BIST (Built In Self Test) controller
Top Level Logic Block Diagram
Port 1 Operation-Control Logic Blocks[1]
UBP1
LBP1
R/WP1
OEP1
CE0P1
CE1P1
CLKP1
18
I/O0P1- I/O17P1
CLKP1
16
A0P1âA15P1
MKLDP1
CNTLDP1
CNTINCP1
CNTRDP1
MKRDP1
CNTRSTP1
INTP1
CNTINTP1
Port-1
Control
Logic
Port 1
I/O
Port 1
Counter/
Mask Reg/
Address
Decode
MRST
TMS
TCK
TDI
CLKBIST
Reset
Logic
JTAG
Controller
BIST
TDO
Port 4 Logic Blocks[2]
Port 1
Port 4
RAM
Array
Port 2
Port 3
Port 2 Logic Blocks[2]
Port 3 Logic Blocks[2]
Notes:
1. Port 1 Control Logic Block is detailed on page 2.
2. Port 2, Port 3, and Port 4 Logic Blocks are similar to Port 1 Logic Blocks.
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation ⢠3901 North First Street ⢠San Jose ⢠CA 95134 ⢠408-943-2600
November 18, 1999
|
▷ |