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CY7C027_05 Datasheet, PDF (1/20 Pages) Cypress Semiconductor – 32K/64K x 16/18 Dual-Port Static RAM | |||
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CY7C027/028
CY7C037/03832K/64K x 16/18 Dual-Port Static RAM
CY7C027/028
CY7C037/038
32K/64K x 16/18 Dual-Port Static RAM
Features
⢠True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
⢠32K x 16 organization (CY7C027)
⢠64K x 16 organization (CY7C028)
⢠32K x 18 organization (CY7C037)
⢠64K x 18 organization (CY7C038)
⢠0.35-micron CMOS for optimum speed/power
⢠High-speed access: 12[1]/15/20 ns
⢠Low operating power
â Active: ICC = 180 mA (typical)
â Standby: ISB3 = 0.05 mA (typical)
⢠Fully asynchronous operation
Logic Block Diagram
R/WL
UBL
⢠Automatic power-down
⢠Expandable data bus to 32/36 bits or more using
Master/Slave chip select when using more than one
device
⢠On-chip arbitration logic
⢠Semaphores included to permit software handshaking
between ports
⢠INT flags for port-to-port communication
⢠Separate upper-byte and lower-byte control
⢠Dual Chip Enables
⢠Pin select for Master or Slave
⢠Commercial and industrial temperature ranges
⢠Available in 100-pin TQFP
⢠Pb-Free packages available
R/WR
UBR
CE0L
CE1L
LBL
OEL
CEL
I/O8/9LâI/O[125] /17L
8/9
I/O0LâI/O[73/]8L
8/9
I/O
Control
I/O
Control
CER
CE0R
CE1R
LBR
OER
8/9
[2]
I/O8/9LâI/O15/17R
8/9
I/O0LâI/O[73/]8R
A0LâA[144]/15L
15/16
Address
Decode
True Dual-Ported
RAM Array
Address
Decode
15/16
A0RâA[144]/15R
A0LâA[144]/15L
15/16
CEL
OEL
R/WL
SEML
BUSYL[5]
INTL
UBL
LBL
Notes:
1. See page 6 for Load Conditions.
2. I/O8âI/O15 for x16 devices; I/O9âI/O17 for x18 devices.
3. I/O0âI/O7 for x16 devices; I/O0âI/O8 for x18 devices.
4. A0âA14 for 32K; A0âA15 for 64K devices.
5. BUSY is an output in master mode and an input in slave mode.
Interrupt
Semaphore
Arbitration
M/S
15/16
A0RâA[144]/15R
CER
OER
R/WR
SEMR
[5] BUSYR
INTR
UBR
LBR
Cypress Semiconductor Corporation ⢠3901 North First Street ⢠San Jose ⢠CA 95134 ⢠408-943-2600
Document #: 38-06042 Rev. *C
Revised June 13, 2005
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