CY7C026A_05 Datasheet, PDF (1/18 Pages) Cypress Semiconductor – 16K x 16/18 Dual-Port Static RAM

CY7C026A
CY7C036A16K x 16/18 Dual-Port Static RAM
CY7C026A
CY7C036A
16K x 16/18 Dual-Port Static RAM
Features
• True dual-ported memory cells that allow simultaneous
access of the same memory location
• 16K x 16 organization (CY7C026A)
• 16K x 18 organization (CY7C036A)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 12^[1]/15/20 ns
• Low operating power
— Active: I_CC = 180 mA (typical)
— Standby: I_SB3 = 0.05 mA (typical)
• Fully asynchronous operation
• Automatic power-down
Logic Block Diagram
• Expandable data bus to 32/36 bits or more using
Master/Slave chip select when using more than one
device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flags for port-to-port communication
• Separate upper-byte and lower-byte control
• Pin select for Master or Slave
• Commercial and Industrial temperature ranges
• Available in 100-Pin TQFP
• Pb-Free packages available
R/W_L
UB_L
R/W_R
UB_R
CE_L
LB_L
OE_L
I/O_8/9L–I/O^[125] _/17L
8/9
I/O_0L–I/O^[73/]8L
8/9
I/O
Control
I/O
Control
CE_R
LB_R
OE_R
8/9
I/O_8/9L–I/O_1[25]/17R
8/9
I/O_0L–I/O^[73/]8R
A_0L–A_13L
14
Address
Decode
True Dual-Ported
RAM Array
Address
14
Decode
A_0R–A_13R
A_0L–A_13L
CE_L
OE_L
R/W_L
SEM_L
BUSY_L ^[4]
INT_L
UB_L
LB_L
14
14
Interrupt
Semaphore
Arbitration
M/S
Notes:
1. See page 6 for Load Conditions.
2. I/O₈–I/O₁₅ for x16 devices; I/O₉–I/O₁₇ for x18 devices.
3. I/O₀–I/O₇ for x16 devices; I/O₀–I/O₈ for x18 devices.
4. BUSY is an output in master mode and an input in slave mode.
A_0R–A_13R
CE_R
OE_R
R/W_R
SEM_R
[4] _BUSYR
INT_R
UB_R
LB_R
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-06046 Rev. *C
Revised September 6, 2005