CY7C026A Datasheet, PDF (1/17 Pages) Cypress Semiconductor – 16K x 16/18 Dual-Port Static RAM

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CY7C026A
CY7C036A
16K x 16/18 Dual-Port Static RAM
Features
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
• 16K x 16 organization (CY7C026A)
• 16K x 18 organization (CY7C036A)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 12^[1]/15/20 ns
• Low operating power
— Active: I_CC = 180 mA (typical)
— Standby: I_SB3 = 0.05 mA (typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 32/36 bits or more using Mas-
ter/Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flags for port-to-port communication
• Separate upper-byte and lower-byte control
• Pin select for Master or Slave
• Commercial and Industrial temperature ranges
• Available in 100-Pin TQFP
• Pin-compatible and functionally equivalent to IDT70261
Logic Block Diagram
R/W_L
UB_L
R/W_R
UB_R
CE_L
LB_L
OE_L
[2]
8/9
I/O_8/9L–I/O_15/17L
[3]
8/9
I/O_0L–I/O_7/8L
I/O
Control
I/O
Control
CE_R
LB_R
OE_R
8/9
[2]
I/O_8/9L–I/O_15/17R
8/9
[3]
I/O_0L–I/O_7/8R
A_0L–A_13L
14
Address
Decode
True Dual-Ported
RAM Array
14
A_0L–A_13L
CE_L
OE_L
R/W_L
SEM_{L [4]}
BUSY_L
INT_L
UB_L
LB_L
Notes:
1. See page 6 for Load Conditions.
2. I/O₈–I/O₁₅ for x16 devices; I/O₉–I/O₁₇ for x18 devices.
3. I/O₀–I/O₇ for x16 devices; I/O₀–I/O₈ for x18 devices.
4. BUSY is an output in master mode and an input in slave mode.
Interrupt
Semaphore
Arbitration
M/S
Address
14
Decode
14
A_0R–A_13R
A_0R–A_13R
CE_R
OE_R
R/W_R
SEM_R
[4]
BUSY_R
INT_R
UB_R
LB_R
For the most recent information, visit the Cypress web site at www.cypress.com
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
March 3, 2000