CY7C024AV_05 Datasheet, PDF (1/19 Pages) Cypress Semiconductor – 3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM

CY7C024AV/025AV/026AV
CY7C0241AV/0251AV/036AV
3.3V 4K/8K/16K x 16/18 Dual-Port Static RAM
Features
• True dual-ported memory cells which allow
simultaneous access of the same memory location
• 4/8/16K × 16 organization (CY7C024AV/025AV/026AV)
• 4/8K × 18 organization (CY7C0241AV/0251AV)
• 16K × 18 organization (CY7C036AV)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 20 and 25 ns
• Low operating power
— Active: I_CC = 115 mA (typical)
— Standby: I_SB3 = 10 μA (typical)
• Fully asynchronous operation
Logic Block Diagram
R/W_L
UB_L
• Automatic power-down
• Expandable data bus to 32/36 bits or more using
Master/Slave chip select when using more than one
device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Separate upper-byte and lower-byte control
• Pin select for Master or Slave
• Commercial and industrial temperature ranges
• Available in 100-pin Lead (Pb)-free TQFP and 100-pin
TQFP
R/W_R
UB_R
CE_L
LB_L
OE_L
[1]
8/9
I/O_8/9L–I/O_15/17L
I/O_0L–I/O^[₇²_/^]_8L
8/9
I/O
Control
I/O
Control
CE_R
LB_R
OE_R
8/9
[1]
I/O_8/9L–I/O_15/17R
8/9
[2]
I/O_0L–I/O_7/8R
[3]
A_0L–A_11/1213L
12/13/14 _Address
Decode
True Dual-Ported
RAM Array
[3]
A_0L–A_11/12/13L
CE_L
OE_L
R/W_L
SEM_{L [4]}
BUSY_L
INT_L
UB_L
LB_L
12/13/14
Interrupt
Semaphore
Arbitration
M/S
Notes:
1. I/O₈–I/O₁₅ for x16 devices; I/O₉–I/O₁₇ for x18 devices.
2. I/O₀–I/O₇ for x16 devices; I/O₀–I/O₈ for x18 devices.
3. A₀–A₁₁ for 4K devices; A₀–A₁₂ for 8K devices; A₀–A₁₃ for 16K devices.
4. BUSY is an output in master mode and an input in slave mode.
Address ^12/13/14
Decode
12/13/14
[3]
A_0R–A_11/12/13R
[3]
A_0R–A_11/12/13R
CE_R
OE_R
R/W_R
[4] ^SEMR
BUSY_R
INT_R
UB_R
LB_R
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-06052 Rev. *H
Revised June 15, 2005