CY7C008V_05 Datasheet, PDF (1/18 Pages) Cypress Semiconductor – 3.3V 64K/128K x 8/9 Dual-Port Static RAM

CY7C008V CY7C018V CY7C009V CY7C019V 3.3V 64K/128K x 8/9
Dual-Port Static RAM
Features
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• 64K x 8 organization (CY7C008)
• 128K x 8 organization (CY7C009)
• 64K x 9 organization (CY7C018)
• 128K x 9 organization (CY7C019)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 15/20/25 ns
• Low operating power
— Active: I_CC = 115 mA (typical)
— Standby: I_SB3 = 10 µA (typical)
• Fully asynchronous operation
Logic Block Diagram
R/W_L
CE_0L
CE_1L
CE_L
OE_L
CY7C008V/009V
CY7C018V/019V
3.3V 64K/128K x 8/9
Dual-Port Static RAM
• Automatic power-down
• Expandable data bus to 16/18 bits or more using
Master/Slave chip select when using more than one
device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Dual Chip Enables
• Pin select for Master or Slave
• Commercial and Industrial Temperature Ranges
• Available in 100-pin TQFP
• Pb-Free packages available
CE_R
R/W_R
CE_0R
CE_1R
OE_R
[1]
8/9
I/O_0L–I/O_7/8L
I/O
Control
I/O
Control
8/9
[1]
I/O_0R–I/O_7/8R
A_0L–A^[125]/16L
16/17
Address
Decode
True Dual-Ported
RAM Array
A_0L–A^[125]/16L
CE_L
OE_L
R/W_L
SEM_L
BUSY_L ^[3]
INT_L
16/17
Notes:
1. I/O₀–I/O₇ for x8 devices; I/O₀–I/O₈ for x9 devices.
2. A₀–A₁₅ for 64K devices; A₀–A₁₆ for 128K.
3. BUSY is an output in master mode and an input in slave mode.
Interrupt
Semaphore
Arbitration
M/S
Address
Decode
16/17
16/17
A_0R–^[2A^]15/16R
A_0R–^[2A^]15/16R
CE_R
OE_R
R/W_R
SEM_R
[3] _BUSYR
INT_R
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-06044 Rev. *C
Revised September 6, 2005