CY7C008 Datasheet, PDF (1/19 Pages) Cypress Semiconductor – 64K/128K x 8/9 Dual-Port Static RAM

CY7C008/009
CY7C018/01964K/128K x 8/9 Dual-Port Static RAM
CY7C008/009
CY7C018/019
64K/128K x 8/9 Dual-Port Static RAM
Features
• True Dual-Ported memory cells which allow simulta-
neous access of the same memory location
• 64K x 8 organization (CY7C008)
• 128K x 8 organization (CY7C009)
• 64K x 9 organization (CY7C018)
• 128K x 9 organization (CY7C019)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 12^[1]/15/20 ns
• Low operating power
— Active: I_CC = 180 mA (typical)
— Standby: I_SB3 = 0.05 mA (typical)
Logic Block Diagram
R/W_L
CE_0L
CE_1L
OE_L
CE_L
[2]
8/9
I/O_0L–I/O_7/8L
I/O
Control
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 16/18 bits or more using Mas-
ter/Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flags for port-to-port communication
• Dual Chip Enables
• Pin select for Master or Slave
• Commercial and Industrial temperature ranges
• Available in 100-pin TQFP
I/O
Control
CE_R
R/W_R
CE_0R
CE_1R
OE_R
8/9
[2]
I/O_0R–I/O_7/8R
[3]
A_0L–A_15/16L
16/17
Address
Decode
True Dual-Ported
RAM Array
[3]
A_0L–A_15/16L
CE_L
OE_L
R/W_L
SEM_{L [4]}
BUSY_L
INT_L
16/17
Notes:
1. See page 6 for Load Conditions.
2. I/O₀–I/O₇ for x8 devices; I/O₀–I/O₈ for x9 devices.
3. A₀–A₁₅ for 64K devices; A₀–A₁₆ for 128K.
4. BUSY is an output in master mode and an input in slave mode.
Interrupt
Semaphore
Arbitration
M/S
Address
Decode
16/17
16/17
[3]
A_0R–A_15/16R
[3]
A_0R–A_15/16R
CE_R
OE_R
R/W_R
SEM_R
[4]
BUSY_R
INT_R
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06041 Rev. *C
Revised June 22, 2004