CY7C006A_13 Datasheet, PDF (1/22 Pages) Cypress Semiconductor – 16 K × 8 Dual-Port Static RAM

CY7C007A16 K × 8 Dual-Port Static RAM
CY7C006A
16 K × 8 Dual-Port Static RAM
16 K × 8 Dual-Port Static RAM
Features
■ True dual-ported memory cells which allow simultaneous
access of the same memory location
■ 16 K × 8 organization (CY7C006A)
■ 0.35-micron CMOS for optimum speed/power
■ High-speed access: 20 ns
■ Low operating power
❐ Active: I_CC = 180 mA (typical)
❐ Standby: I_SB3 = 0.05 mA (typical)
■ Fully asynchronous operation
■ Automatic power-down
Logic Block Diagram
R/W_L
CE_L
OE_L
8
I/O_0L–I/O_7L
I/O
Control
■ Expandable data bus to 16 bits or more using
Master/Slave chip select when using more than one
device
■ On-chip arbitration logic
■ Semaphores included to permit software handshaking
between ports
■ INT flags for port-to-port communication
■ Pin select for Master or Slave
■ Commercial temperature range
■ Available in 68-pin PLCC (CY7C006A), 64-pin TQFP
(CY7C006A)
■ Pb-free packages available
I/O
Control
R/W_R
CE_R
OE_R
8
I/O_0R–I/O_7R
A_0L–A_13L
A_0L–A_13L
CE_L
OE_L
R/W_L
SEM_L
BUSY_L ^[1]
INT_L
14
Address
Decode
14
True Dual-Ported
RAM Array
Interrupt
Semaphore
Arbitration
M/S
Address
14
Decode
14
A_0R–A_13R
A_0R–A_13R
CE_R
OE_R
R/W_R
SEM_R
[1] _BUSYR
INT_R
Note
1. BUSY is an output in master mode and an input in slave mode.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-06045 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 30, 2013