CY7C006A Datasheet, PDF (1/20 Pages) Cypress Semiconductor – 32K/16K x8, 32K/16K x9 Dual-Port Static RAM

CY7C006A
CY7C007A
CY7C017A32K/16K x 8, 32K x 9
Dual-Port Static RAM
Features
• True dual-ported memory cells which allow
simultaneous access of the same memory location
• 16K x 8 organization (CY7C006A)
• 32K x 8 organization (CY7C007A)
• 16K x 9 organization (CY7C016A)
• 32K x 9 organization (CY7C017A)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 12^[1]/15/20 ns
• Low operating power
— Active: I_CC = 180 mA (typical)
— Standby: I_SB3 = 0.05 mA (typical)
• Fully asynchronous operation
Logic Block Diagram
R/W_L
CE_L
OE_L
[2]
8/9
I/O_0L–I/O_7/8L
I/O
Control
CY7C006A/CY7C007A
CY7C016A/CY7C017A
32K/16K x8, 32K/16K x9
Dual-Port Static RAM
• Automatic power-down
• Expandable data bus to 16/18 bits or more using
Master/Slave chip select when using more than one
device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flags for port-to-port communication
• Pin select for Master or Slave
• Commercial temperature range
• Available in 68-pin PLCC (CY7C006A, CY7C007A and
CY7C017A), 64-pin TQFP (CY7C006A), and in 80-pin
TQFP (CY7C007A and CY7C016A)
I/O
Control
R/W_R
CE_R
OE_R
8/9
[2]
I/O_0R–I/O_7/8R
A_0L–A_13/1[44L]
14/15
Address
Decode
True Dual-Ported
RAM Array
Address
Decode
14/15
A_0R–A_13/14[R4]
A_0L–A_13/14[4L]
CE_L
OE_L
R/W_L
SEM_L
BUSY_L ^[3]
INT_L
14/15
Interrupt
Semaphore
Arbitration
M/S
For the most recent information, visit the Cypress web site at www.cypress.com
Notes:
1. See page 7 for Load Conditions.
2. I/O₀–I/O₇ for x8 devices; I/O₀–I/O₈ for x9 devices.
3. BUSY is an output in master mode and an input in slave mode.
4. A₀–A₁₃ for 16K; A₀–A₁₄ for 32K devices.
14/15
A_0R–A_13/14R[4]
CE_R
OE_R
R/W_R
SEM_R
[3] _BUSYR
INT_R
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06045 Rev. *C
Revised April 11, 2005