CY7B995 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 2.5/3.3V 200-MHz High-Speed Multi-Phase PLL Clock Buffer

CY7B995
2.5/3.3V 200-MHz High-Speed Multi-Phase
PLL Clock Buffer
Features
Description
• 2.5V or 3.3V operation
• Split output bank power supplies
• Output frequency range: 6 MHz to 200 MHz
• Output-output skew < 100 ps
• Cycle-cycle jitter <100 ps
• ± 2% max output duty cycle
• Selectable output drive strength
• Selectable positive or negative edge synchronization
• Eight LVTTL outputs driving 50Ω terminated lines
• LVCMOS/LVTTL over-voltage tolerant reference input
• Selectable phase-locked loop (PLL) frequency range
and lock indicator
• Phase adjustments in 625/1250 ps steps up to ± 7.5 ns
• (1-6,8,10,12) x multiply and (1/2,1/4)x divide ratios
• Spread-Spectrum-compatible
• Power-down mode
• Selectable reference divider
• Industrial temperature range: -40°C to +85°C
• 44-pin TQFP package
The CY7B995 RoboClock is a low-voltage, low-power,
eight-output, 200-MHz clock driver. It features output phase
programmability which is necessary to optimize the timing of
high-performance computer and communication systems.
The user can program both the frequency and the phase of the
output banks through nF[0:1] and DS[0:1] pins. The adjustable
phase feature allows the user to skew the outputs to lead or
lag the reference clock. Any one of the outputs can be con-
nected to feedback input to achieve different reference fre-
quency multiplication and divide ratios and zero input-output
delay.
The device also features split output bank power supplies
which enable the user to run two banks (1Qn and 2Qn) at a
power supply level different from that of the other two banks
(3Qn and 4Qn). Additionally, the three-level PE/HD pin con-
trols the synchronization of the output signals to either the ris-
ing or the falling edge of the reference clock and selects the
drive strength of the output buffers. The high drive option
(PE/HD = MID) increases the output current from ± 12 mA to
± 24 mA
(3.3V).
Block Diagram
PD#/DIV
REF
FB
DS1:0
1F1:0
TEST PE/HD FS VDDQ1
3
/R
/N
3
3
3
3
3
PLL
3
Phase
3 Select
2F1:0
3F1:0
4F1:0
3
Phase
3 _Select
3 _Phase
3 ^Select
and /K
3 _Phase
Select
3 _{and /M}
Pin Configuration
LOCK
1Q0
1Q1
2Q0
2Q1
3Q0
3Q1
VDDQ3
4Q0
4Q1
4F1
sOE#
PD#/DIV
PE/HD
VDDQ4
VDDQ4
4Q1
4Q0
VSS
VSS
VSS
44 43 42 41 40 39 38 37 36 35 34
1
33
2
32
3
31
4
30
5
29
6
CY7B995
28
7
27
8
26
9
25
10
24
11
23
12 13 14 15 16 17 18 19 20 21 22
1F0
DS1
DS0
LOCK
VDDQ1
VDDQ1
1Q0
1Q1
VSS
VSS
VSS
VDDQ4 sOE#
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07337 Rev. *A
Revised February 24, 2004