CY7B9945V Datasheet, PDF (1/10 Pages) Cypress Semiconductor – High-speed Multi-phase PLL Clock Buffer

RoboClock^
CY7B9945V
High-speed Multi-phase PLL Clock Buffer
Features
• 500 ps max. Total Timing Budget™ (TTB™) window
• 24–200 MHz input/output operation
• Low output-output skew < 200 ps
• 10 + 1 LVTTL outputs driving 50Ω terminated lines
• Dedicated feedback output
• Phase adjustments in 625/1300 ps steps up to +10.4 ns
• 3.3V LVTTL/LVPECL, fault-tolerant, and hot-insertable
reference inputs
• Multiply/divide ratios of 1–6, 8, 10, and 12
• Individual output bank disable
• Output high-impedance option for testing purposes
• Integrated phase-locked loop (PLL) with lock indicator
• Low cycle-cycle jitter (<100 ps peak-peak)
• 3.3V operation
• Industrial temperature range: –40°C to +85°C
• 52-pin 1.4-mm TQFP package
Functional Description
The CY7B9945V high-speed multi-phase PLL clock buffer
offers user-selectable control over system clock functions.
Block Diagram
FS
3
This multiple-output clock driver provides the system
integrator with functions necessary to optimize the timing of
high-performance computer and communication systems.
The device features a guaranteed maximum TTB window
specifying all occurrences of output clocks with respect to the
input reference clock across variations in output frequency,
supply voltage, operating temperature, input edge rate, and
process.
Ten configurable outputs each drive terminated transmission
lines with impedances as low as 50Ω while delivering minimal
and specified output skews at LVTTL levels. The outputs are
arranged in two banks of four and six outputs. These banks
allow a divide function of 1 to 12, with phase adjustments in
625-ps–1300-ps increments up to ±10.4 ns. The dedicated
feedback output allows divide-by functionality from 1 to 12 and
limited phase adjustments. However, if needed, any one of the
ten outputs can be connected to the feedback input as well as
driving other inputs.
Selectable reference input is a fault-tolerant feature which
allows smooth change over to secondary clock source, when
the primary clock source is not in operation. The reference
inputs and feedback inputs are configurable to accommodate
both LVTTL or Differential (LVPECL) inputs. The completely
integrated PLL reduces jitter and simplifies board layout.
Pin Configuration
REFA+
REFA-
REFB+
REFB-
REFSEL
FBK
MODE
PLL
LOCK
FBF0
3
Divide
and
FBDS0
3
Phase
QF
FBDS1
3
Select
1F0
3
1Q0
1F1
3
1Q1
1DS0
3
Divide
and
1DS1
3
Phase
Select
1F2
3
1Q2
1F3
3
1Q3
DIS1
2Q0
2F0
3
2Q1
Divide
2F1
3
and
2Q2
2DS0
3
Phase
2Q3
Select
2DS1
3
2Q4
2Q5
DIS2
2F1
2F0
2DS1
GND
2Q0
VCCN
2Q1
2Q2
VCCN
2Q3
GND
1DS1
2DS0
52 51 50 49 48 47 46 45 44 43 42 41 40
1
39
2
38
3
37
4
36
5
35
6
7
CY7B9945V
34
33
8
32
9
31
10
30
11
29
12
28
13
27
14 15 16 17 18 19 20 21 22 23 24 25 26
REFA-
REFSEL
REFB-
REFB+
1F2
FS
GND
1Q2
VCCN
1Q3
FBF0
1F0
VCCQ
Cypress Semiconductor Corporation •
Document #: 38-07336 Rev. *D
3901 North First Street • San Jose, CA 95134 • 408-943-2600
Revised July 24, 2003