CY7B9911V Datasheet, PDF (1/11 Pages) Cypress Semiconductor – High-Speed Low-Voltage Programmable Skew Clock Buffer LV-PSCB

CY7B9911V
3.3V RoboClock+
High-Speed Low-Voltage Programmable Skew Clock Buffer
(LV-PSCB)
Features
• All output pair skew <100 ps typical (250 max.)
• 3.75- to 110-MHz output operation
• User-selectable output functions
— Selectable skew to 18 ns
— Inverted and non-inverted
— Operation at ¹â„₂ and ¹â„₄ input frequency
— Operation at 2x and 4x input frequency (input as low
as 3.75 MHz)
• Zero input-to-output delay
• 50% duty-cycle outputs
• LVTTL outputs drive 50Ω terminated lines
• Operates from a single 3.3V supply
• Low operating current
• 32-pin PLCC package
• Jitter < 200 ps peak-to-peak (< 25 ps RMS)
Functional Description
The CY7B9911V 3.3V RoboClock+ High-Speed Low-Voltage
Programmable Skew Clock Buffer (LVPSCB) offers user-
selectable control over system clock functions. These multiple-
output clock drivers provide the system integrator with func-
tions necessary to optimize the timing of high-performance
computer systems. Eight individual drivers, arranged as four
pairs of user-controllable outputs, can each drive terminated
transmission lines with impedances as low as 50Ω while deliv-
ering minimal and specified output skews and full-swing logic levels
(LVTTL).
Each output can be hardwired to one of nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are deter-
mined by the operating frequency with outputs able to skew up
to ±6 time units from their nominal “zero” skew position. The com-
pletely integrated PLL allows external load and transmission
line delay effects to be canceled. When this “zero delay” capa-
bility of the LVPSCB is combined with the selectable output
skew functions, the user can create output-to-output delays of
up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low-frequency clock that can be multi-
plied by two or four at the clock destination. This facility mini-
mizes clock distribution difficulty while allowing maximum sys-
tem clock speed and flexibility.
Logic Block Diagram
Pin Configuration
TEST
FB
REF
PHASE
FREQ _FILTER
DET
FS
VCO AND
TIME UNIT
GENERATOR
4F0
4F1
SELECT
INPUTS
(THREE
LEVEL)
3F0
3F1
2F0
2F1
SKEW
SELECT
MATRIX
PLCC
4 3 2 1 32 31 30
3F1 5
29 2F0
4Q0
4F0 6
28 GND
4F1 ₇
27 1F1
4Q1
V_CCQ 8
26 1F0
3Q0
V_CCN 9
CY7B9911V
25 V_CCN
4Q1 10
3Q1
4Q0 11
24 1Q0
23 1Q1
2Q0
GND 12
22 GND
GND 13
21 GND
2Q1
14 15 16 17 18 19 20
1F0
1Q0
1F1
1Q1
7B9911V–1
7B9911V–2
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
December 1, 1999