CY7B991 Datasheet, PDF (1/15 Pages) Cypress Semiconductor – Programmable Skew Clock Buffer

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CY7B991
CY7B992
Programmable Skew Clock Buffer
Features
• All output pair skew <100 ps typical (250 max.)
• 3.75- to 80-MHz output operation
• User-selectable output functions
— Selectable skew to 18 ns
— Inverted and non-inverted
— Operation at ¹â„₂ and ¹â„₄ input frequency
— Operation at 2x and 4x input frequency (input as low
as 3.75 MHz)
• Zero input to output delay
• 50% duty-cycle outputs
• Outputs drive 50Ω terminated lines
• Low operating current
• 32-pin PLCC/LCC package
• Jitter < 200 ps peak-to-peak (< 25 ps RMS)
• Compatible with a Pentium™-based processor
Functional Description
The CY7B991 and CY7B992 Programmable Skew Clock Buff-
ers (PSCB) offer user-selectable control over system clock
functions. These multiple-output clock drivers provide the sys-
tem integrator with functions necessary to optimize the timing
of high-performance computer systems. Eight individual driv-
ers, arranged as four pairs of user-controllable outputs, can
each drive terminated transmission lines with impedances as
low as 50Ω while delivering minimal and specified output skews
and full-swing logic levels (CY7B991 TTL or CY7B992 CMOS).
Each output can be hardwired to one of nine delay or function
configurations. Delay increments of 0.7 to 1.5 ns are deter-
mined by the operating frequency with outputs able to skew up
to ±6 time units from their nominal “zero” skew position. The com-
pletely integrated PLL allows external load and transmission line
delay effects to be canceled. When this “zero delay” capability of the
PSCB is combined with the selectable output skew functions, the
user can create output-to-output delays of up to ±12 time units.
Divide-by-two and divide-by-four output functions are provided
for additional flexibility in designing complex clock systems.
When combined with the internal PLL, these divide functions
allow distribution of a low-frequency clock that can be multi-
plied by two or four at the clock destination. This facility mini-
mizes clock distribution difficulty while allowing maximum sys-
tem clock speed and flexibility.
Logic Block Diagram
Pin Configuration
TEST
FB
REF
PHASE
FREQ _FILTER
DET
FS
VCO AND
TIME UNIT
GENERATOR
4F0
4F1
SELECT
INPUTS
(THREE
LEVEL)
3F0
3F1
2F0
2F1
SKEW
SELECT
MATRIX
PLCC/LCC
4 3 2 1 32 31 30
3F1 5
29 2F0
4Q0
4F0 6
28 GND
4F1 ₇
27 1F1
4Q1
V_CCQ 8
26 1F0
CY7B991
3Q0
V_CCN 9
CY7B992
25 V_CCN
4Q1 10
3Q1
4Q0 11
24 1Q0
23 1Q1
2Q0
GND 12
22 GND
GND 13
21 GND
2Q1
14 15 16 17 18 19 20
1F0
1Q0
1F1
1Q1
Pentium is a trademark of Intel Corporation.
7B991–1
7B991–2
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-07138 Rev. **
Revised September 26, 2001