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CY7B952_11 Datasheet, PDF (1/16 Pages) Cypress Semiconductor – SST™ SONET/SDH Serial Transceiver | |||
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CY7B952
SST⢠SONET/SDH Serial Transceiver
SST⢠SONET/SDH Serial Transceiver
Features
â OC-3 Compliant with Bellcore and CCITT (ITU) specifications
on:
â Jitter Generation (<0.01 UI)
â Jitter Transfer (<130 kHz)
â Jitter Tolerance
â SONET/SDH and ATM Compliant
â Compatible with IGT WAC013, IGT WAC413, and PMC-Sierra
PM5343
â Clock and data recovery from 51.84- or 155.52-MHz
datastream
â 155.52-MHz clock multiplication from 19.44-MHz source
â 51.84-MHz clock multiplication from 6.48-MHz source
â ï±1% frequency agility
â Line Receiver Inputs: No external buffering required
â Differential output buffering
â 100K ECL compatible I/O
â No output clock âdriftâ without data transitions
â Link Status Indication
â Loop-back testing
â Single +5 V supply
â 24-pin SOIC
â Compatible with fiber-optic modules, coaxial cable, and twisted
pair media
â Power-down options to minimize power or crosstalk
â Low operating current: <70 mA
â 0.8ï BiCMOS
Functional Description
The SONET/SDH Serial Transceiver (SST) is used in
SONET/SDH and ATM applications to recover clock and data
information from a 155.52-MHz or 51.84-MHz NRZ or NRZI
serial data stream and to provide differential data buffering for
the Transmit side of the system.
Logic Block Diagram
LOOP(t)
MODE
FC+
FCâ
RIN+
RINâ
CD
PLL
RECEIVE
TRANSMIT
RCLK+
RCLKâ
RSER+
RSERâ
LFI(t)
TOUT+
TOUTâ
TSER+
TSERâ
PLL
x8
TCLK+
TCLKâ
REFCLK+
REFCLKâ
Cypress Semiconductor Corporation ⢠198 Champion Court
Document Number: 38-02018 Rev. *E
⢠San Jose, CA 95134-1709 ⢠408-943-2600
Revised November 9, 2011
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