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CY7B952 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – SSTTM SONET/SDH Serial Transceiver | |||
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CY7B952
SST⢠SONET/SDH Serial Transceiver
Features
⢠100K ECL compatible I/O
⢠OC-3 Compliant with Bellcore and CCITT (ITU) specifi-
cations on:
â Jitter Generation (<0.01 UI)
â Jitter Transfer (<130 kHz)
â Jitter Tolerance
⢠SONET/SDH and ATM Compliant
⢠Compatible with IGT WAC013, IGT WAC413, and
PMC-Sierra PM5343
⢠Clock and data recovery from 51.84- or 155.52-MHz
datastream
⢠155.52-MHz clock multiplication from 19.44-MHz source
⢠No output clock âdriftâ without data transitions
⢠Link Status Indication
⢠Loop-back testing
⢠Single +5V supply
⢠24-pin SOIC
⢠Compatible with fiber-optic modules, coaxial cable, and
twisted pair media
⢠Power-down options to minimize power or crosstalk
⢠Low operating current: <70 mA
⢠0.8µ BiCMOS
⢠51.84-MHz clock multiplication from 6.48-MHz source Functional Description
⢠±1% frequency agility
⢠Line Receiver Inputs: No external buffering required
⢠Differential output buffering
The SONET/SDH Serial Transceiver (SST) is used in
SONET/SDH and ATM applications to recover clock and data
information from a 155.52-MHz or 51.84-MHz NRZ or NRZI
serial data stream and to provide differential data buffering for
the Transmit side of the system.
Logic Block Diagram LOOP(t)
MODE
FC+
FCâ
RIN+
RINâ
PLL
CD
TOUT+
TOUTâ
RECEIVE
TRANSMIT
PLL
x8
Pin Configuration
RCLK+
RCLKâ
RSER+
RSERâ
LFI(t)
TSER+
TSERâ
FC+
FCâ
RIN+
RINâ
MODE
VCC
CD
LOOP
REFCLKâ
REFCLK+
TOUTâ
TOUT+
SOIC
Top View
1
24
2
23
3
22
4
21
5
20
6 CY7B952 19
7
18
8
17
9
16
10
15
11
14
12
13
TCLK+
TCLKâ
RCLKâ
RCLK+
RSERâ
RSER+
LFI
VCC
VSS
VCC
TCLKâ
TCLK+
TSER+
TSERâ
REFCLK+
REFCLKâ
SST
Clock/Data
Recovery
Line
Driver
S->P
P->S
SONET/SDH
Transport
Overhead
Transceiver
SONET/SDH
Path
Overhead
Transceiver
Cypress
CY7B952
PMC-Sierra
PM5343STXC
PMC-Sierra
PM5344SPTX
Figure 1. SONET/SDH Overhead Processing Application
Cypress Semiconductor Corporation ⢠3901 North First Street ⢠San Jose, CA 95134 ⢠408-943-2600
Document #: 38-02018 Rev. *B
Revised April 27, 2004
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