CY7B923_05 Datasheet, PDF (1/33 Pages) Cypress Semiconductor – HOTLink Transmitter/Receiver

CY7B923
CY7B933
HOTLink^ Transmitter/Receiver
Features
• Fibre-Channel-compliant
• IBM ESCON^-compliant
• DVB-ASI-compliant
• ATM-compliant
• 8B/10B-coded or 10-bit unencoded
• Standard HOTLink^: 160–330 Mbps
• High-speed HOTLink: 160–400 Mbps for high-speed
applications
• Low-speed HOTLink: 150–160 Mbps for low-cost fiber
applications
• TTL synchronous I/O
• No external phase locked-loop (PLL) components
• Triple PECL 100K serial outputs
• Dual PECL 100K serial inputs
• Low power: 350 mW (Tx), 650 mW (Rx)
• Compatible with fiber-optic modules, coaxial cable, and
twisted pair media
• Built-in Self-Test (BIST)
• Single +5V supply
• 28-pin SOIC/PLCC/LCC
• Pb-Free Packages Available
• 0.8µ BiCMOS
Functional Description
The CY7B923 HOTLink^‚ Transmitter and CY7B933 HOTLink
Receiver are point-to-point communications building blocks
that transfer data over high-speed serial links (fiber, coax, and
twisted pair). Standard HOTLink data rates range from 160 to
330 Mbits/second. Higher speed HOTLink is also available for
high-speed applications (160–400 Mbits/second), as well as,
for low-cost applications, HOTLink-155 (150–160
Mbits/second operations). Figure 1 illustrates typical connec-
tions to host systems or controllers.
Eight bits of user data or protocol information are loaded into
the HOTLink transmitter and are encoded. Serial data is
shifted out of the three differential positive ECL (PECL) serial
ports at the bit rate (which is ten times the byte rate).
The HOTLink receiver accepts the serial bit stream at its differ-
ential line receiver inputs and, using a completely integrated
PLL Clock Synchronizer, recovers the timing information
necessary for data reconstruction. The bit stream is deseri-
alized, decoded, and checked for transmission errors.
Recovered bytes are presented in parallel to the receiving host
along with a byte-rate clock.
The 8B/10B encoder/decoder can be disabled in systems that
already encode or scramble the transmitted data. I/O signals
are available to create a seamless interface with both
asynchronous FIFOs (i.e., CY7C42X) and clocked FIFOs (i.e.,
CY7C44X). A BIST pattern generator and checker allows
testing of the transmitter, receiver, and the connecting link as
a part of a system diagnostic check.
HOTLink devices are ideal for a variety of applications where
a parallel interface can be replaced with a high-speed
point-to-point serial link. Applications include interconnecting
workstations, servers, mass storage, and video transmission
equipment.
CY7B923 Transmitter Logic Block Diagram
RP ENN ENA
SC/D (Da)
D_0–7
(D_b–h)
SVS(Dj)
FOTO
CKW
ENABLE
INPUT REGISTER
CLOCK
GENERATOR
MODE
BISTEN
TEST
LOGIC
ENCODER
SHIFTER
OUTA
OUTB
OUTC
CY7B933 Receiver Logic Block Diagram
RF
A/B
INA+
INA−
INB (INB+)
SI(INB− )
SO
REFCLK
MODE
BISTEN
FRAMER
PECL
TTL
CLOCK
SYNC
DATA _SHIFTER
DECODER
REGISTER
DECODER
TEST
LOGIC
OUTPUT
REGISTER
CKR
RDY
Q_0–7
(Q_b–h)
RVS(Qj)
SC/D (Qa)
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-02017 Rev. *E
Revised August 29, 2005