CY7B9234_07 Datasheet, PDF (1/34 Pages) Cypress Semiconductor – SMPTE HOTLink™ Transmitter/Receiver

PRELIMINARY
CY7B9234
CY7B9334
SMPTE HOTLink™ Transmitter/Receiver
1CY7B 9334
Features
• SMPTE-259M-BCD compliant along with SMPTE-259M
encoder (CY7C9235) and decoder (CY7C9335)
• Fibre Channel compliant
• DVB-ASI compliant
• RX PLL tolerant of long run length data patterns (>20
bits)
• 8B/10B-coded or 10-bit unencoded
• TTL synchronous I/O
• No external PLL components
• Triple PECL 100K serial outputs
• Dual PECL 100K serial inputs
• Low power: 350 mW (Tx), 650 mW (Rx)
• Compatible with fiber-optic modules, coaxial cable, and
twisted pair media
• Built-In Self-Test
• Single +5V supply
• 28-pin PLCC
• 0.8µ BiCMOS
Functional Description
The CY7B9234 SMPTE HOTLink™ Transmitter and
CY7B9334 SMPTE HOTLink Receiver bolt on to the SMPTE
Scrambler Controller (CY7C9235) and SMPTE Descram-
bler/Framer Controller (CY7C9335) completing the four piece
chipset to transfer uncompressed SMPTE-259M encoded vid-
eo over high-speed serial links (fiber, coax, and twisted pair).
SMPTE HOTLink supports SMPTE-259M-BCD standard data
rates at 177, 270, and 360 Mbps. Figure 1 illustrates typical
connections to host systems or controllers.
Eight or ten bits of user data or protocol information are loaded
into the SMPTE HOTLink transmitter and, in DVB mode, are
encoded. Serial data is shifted out of the three differential pos-
itive ECL (PECL) serial ports at the bit rate (which is 10 times
the byte rate).
The SMPTE HOTLink receiver accepts the serial bit stream at
its differential line receiver inputs and, using a completely in-
tegrated PLL Clock Synchronizer, recovers the timing informa-
tion necessary for data reconstruction. The bit stream is dese-
rialized, and in DVB mode, decoded and checked for
transmission errors. Recovered bytes are presented in parallel
to the receiving host along with a byte rate clock.
The 8B/10B encoder/decoder can be disabled in SMPTE or
DVB systems that already encode or scramble the transmitted
data. I/O signals are available to create a seamless interface
with both asynchronous FIFOs (i.e., CY7C42X) and clocked
FIFOs (i.e., CY7C44X). A Built-In Self-Test pattern generator
and checker allows testing of the transmitter, receiver, and the
connecting link as a part of a system diagnostic check.
SMPTE HOTLink devices are ideal for a variety of video appli-
cations including video transmission equipment, video record-
ers, video editing equipment, and video routers.
CY7B9234 Transmitter Logic Block Diagram
RP ENN ENA
SC/D (D_a)
D_{0− 7}
(D_{b − h})
SVS(D_j)
FOTO
CKW
ENABLE
INPUT REGISTER
CLOCK
GENERATOR
MODE
BISTEN
TEST
LOGIC
ENCODER
SHIFTER
OUTA
OUTB
OUTC
B9234–1
CY7B9334 Receiver Logic Block Diagram
RF
A/B
INA+
INA−
INB (INB+)
SI(INB− )
SO
REFCLK
FRAMER
PECL
TTL
CLOCK
SYNC
DATA _SHIFTER
DECODER
REGISTER
DECODER
MODE
BISTEN
TEST
LOGIC
OUTPUT
REGISTER
HOTLink is a trademark of Cypress Semiconductor Corporation.
ESCON is a registered trademark of IBM.
CKR
RDY
Q_{0− 7}
(Q_{b − h})
RVS(Q_j)
SC/D (Q_a) ^B9234–2
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-02014 Rev. **
Revised March 19, 1999