CY62187EV30 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – 64 Mbit (4M x 16) Static RAM

CY62187EV30, MoBL^®
64 Mbit (4M x 16) Static RAM
Features
■ Very High Speed
❐ 55 ns
■ Wide Voltage Range
❐ 2.2V to 3.7V
■ Ultra Low Standby Power
❐ Typical Standby Current: 8 μA
❐ Maximum Standby Current: 48 μA
■ Ultra Low Active Power
❐ Typical Active Current: 4.0 mA at f = 1 MHz
■ Easy Memory Expansion with CE₁, CE_2, and OE Features
■ Automatic Power Down when Deselected
■ CMOS for Optimum Speed and Power
■ Available in Pb-Free 48-Ball FBGA Package
Functional Description
The CY62187EV30 is a high performance CMOS static RAM
organized as 4M words by 16 bits^[1]. This device features
advanced circuit design to provide ultra low active current. It is
ideal for providing More Battery Life™ (MoBL^®) in portable appli-
cations such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption by 99 percent when addresses are not toggling.
The device can also be put into standby mode when deselected
(CE₁ HIGH or CE₂ LOW or both BHE and BLE are HIGH). The
input and output pins (IO₀ through IO₁₅) are placed in a high
impedance state when: deselected (CE₁HIGH or CE₂ LOW),
outputs are disabled (OE HIGH), both Byte High Enable and
Byte Low Enable are disabled (BHE, BLE HIGH), or during a
write operation (CE₁ LOW, CE₂ HIGH and WE LOW).
To write to the device, take Chip Enables (CE₁ LOW and CE₂
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (IO₀ through IO₇), is
written into the location specified on the address pins (A₀ through
A₂₁). If Byte High Enable (BHE) is LOW, then data from I/O pins
(IO₈ through IO₁₅) is written into the location specified on the
address pins (A₀ through A₂₁).
To read from the device, take Chip Enables (CE₁ LOW and CE₂
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appear
on IO₀ to IO₇. If Byte High Enable (BHE) is LOW, then data from
memory appears on IO₈ to IO₁₅. See the Truth Table on page 9
for a complete description of read and write modes.
Logic Block Diagram
A₁₀
A₉
A₈
A₇
A₆
A₅
A₄
A₃
A₂
A₁
A₀
DATA-IN DRIVERS
4096K × 16
RAM Array
I/O₀–I/O₇
I/O₈–I/O₁₅
COLUMN DECODER
Power-down
Circuit
BHE
WE
OE
BLE
CE₂
CE₁
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-48998 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 10, 2009
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