CY62177EV30 Datasheet, PDF (1/14 Pages) Cypress Semiconductor – 32-Mbit (2 M × 16 / 4 M × 8) Static RAM

CY62177EV30 MoBL^®
32-Mbit (2 M × 16 / 4 M × 8) Static RAM
32-Mbit (2 M × 16 / 4 M × 8) Static RAM
Features
■ Thin small outline package (TSOP) I configurable as 2 M × 16
or as 4 M x 8 static RAM (SRAM)
■ Very high speed
❐ 55 ns
■ Wide voltage range
❐ 2.2 V to 3.7 V
■ Ultra low standby power
❐ Typical standby current: 3 A
❐ Maximum standby current: 25 A
■ Ultra low active power
❐ Typical active current: 4.5 mA at f = 1 MHz
■ Easy memory expansion with CE₁, CE_2, and OE Features
■ Automatic power down when deselected
■ Complementary Metal Oxide Semiconductor (CMOS) for
optimum speed and power
■ Available in Pb-free 48-ball TSOP I package
Logic Block Diagram
A₁₀
A₉
A
A
A
8
7
6
A₅
A₄
A₃
A₂
A
A
1
0
DATA IN DRIVERS
2M × 16
RAM Array
Functional Description
The CY62177EV30 is a high performance CMOS static RAM
organized as 2 M words by 16 bits and 4 M words by 8 bits^[1].
This device features advanced circuit design to provide ultra low
active current. It is ideal for providing More Battery Life
(MoBL^®) in portable applications such as cellular telephones.
The device also has an automatic power down feature that
significantly reduces power consumption by 99 percent when
addresses are not toggling. The device can also be put into
standby mode when deselected (CE₁ HIGH or CE₂ LOW or both
BHE and BLE are HIGH). The input and output pins (I/O₀ through
I/O₁₅) are placed in a high impedance state when: deselected
(CE₁HIGH or CE₂ LOW), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE, BLE
HIGH), or during a write operation (CE₁ LOW, CE₂ HIGH and WE
LOW).
To write to the device, take Chip Enables (CE₁ LOW and CE₂
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O₀ through I/O₇), is
written into the location specified on the address pins (A₀ through
A₂₀). If Byte High Enable (BHE) is LOW, then data from I/O pins
(I/O₈ through I/O₁₅) is written to the location specified on the
address pins (A₀ through A₂₀). To read from the device, take
Chip Enables (CE₁ LOW and CE₂ HIGH) and Output Enable
(OE) LOW while forcing the Write Enable (WE) HIGH. If Byte
Low Enable (BLE) is LOW, then data from the memory location
specified by the address pins appear on I/O₀ to I/O₇. If Byte High
Enable (BHE) is LOW, then data from memory appears on I/O₈
to I/O₁₅. See the Truth Table on page 10 for a complete
description of read and write modes.
Pin
left
#13 of
floating
the 48 TSOP
at all times to
IepnascukreagperoispearnaDppNliUcaptiionnt_.hat
must
be
I/O₀–I/O₇
I/O₈–I/O₁₅
COLUMN DECODER
Power-Down
Circuit
BHE
BLE
BYTE
BHE
WE
OE
BLE
CE₂
CE₁
CE₂
CE₁
Note
1. For best practice recommendations, refer to the Cypress application note System Design Guidelines.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-09880 Rev. *G
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 22, 2011
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