CY62177DV30_11 Datasheet, PDF (1/14 Pages) Cypress Semiconductor – 32-Mbit (2M x 16) Static RAM

CY62177DV30 MoBL^®
32-Mbit (2M x 16) Static RAM
Features
■ Very high speed: 55 ns
■ Wide voltage range: 2.20 V–3.60 V
■ Ultra-low active power
❐ Typical active current: 2 mA @ f = 1 MHz
❐ Typical active current: 15 mA @ f = f_max
■ Ultra low standby power
■ Easy memory expansion with CE₁, CE₂ and OE features
■ Automatic power-down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed/power
■ Packages offered in a 48-ball fine ball grid array (FBGA)
Functional Description^[1]
The CY62177DV30 is a high-performance CMOS static RAM
organized as 2M words by 16 bits. This device features
advanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life (MoBL^®) in portable
Logic Block Diagram
A₁₀
A₉
A
A
A
8
7
6
A₅
A₄
A₃
A₂
A
A
1
0
DATA-IN DRIVERS
2048K × 16
RAM Array
applications such as cellular telephones.The device also has an
automatic power-down feature that significantly reduces power
consumption. The device can also be put into standby mode
when deselected (CE₁ HIGH or CE₂ LOW or both BHE and BLE
are HIGH). The input/output pins (I/O₀ through I/O₁₅) are placed
in a high-impedance state when: deselected (CE₁HIGH or CE₂
LOW), outputs are disabled (OE HIGH), both Byte High Enable
and Byte Low Enable are disabled (BHE, BLE HIGH), or during
a write operation (CE₁ LOW, CE₂ HIGH and WE LOW).
Writing to the device is accomplished by taking Chip Enables
(CE₁ LOW and CE₂ HIGH) and Write Enable (WE) input LOW. If
Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O₀
through I/O₇), is written into the location specified on the address
pins (A₀ through A₂₀). If Byte High Enable (BHE) is LOW, then
data from I/O pins (I/O₈ through I/O₁₅) is written into the location
specified on the address pins (A₀ through A₂₀).
Reading from the device is accomplished by taking Chip Enables
(CE₁ LOW and CE₂ HIGH) and Output Enable (OE) LOW while
forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE)
is LOW, then data from the memory location specified by the
address pins will appear on I/O₀ to I/O₇. If Byte High Enable
(BHE) is LOW, then data from memory will appear on I/O₈ to
I/O₁₅. See the truth table for a complete description of read and
write modes.
I/O₀–I/O₇
I/O₈–I/O₁₅
COLUMN DECODER
Power-down
Circuit
BHE
WE
OE
BLE
CE₂
CE₁
Note
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number : 38-05633 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 25, 2011
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