CY62177DV20_08 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 32-Mbit (2M x 16) Static RAM

CY62177DV20 MoBL2™
32-Mbit (2M x 16) Static RAM
Features
■ Very high speed: 70 ns
■ Wide voltage range: 1.7V – 2.2V
■ Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
❐ Typical active current: 12 mA at f = f_MAX
■ Ultra low standby power
■ Easy memory expansion with CE₁, CE₂, and OE features
■ Automatic power down when deselected
■ CMOS for optimum speed and power
■ Offered in 48-ball VFBGA package
Functional Description
The CY62177DV20 is a high performance CMOS static RAM
organized as 2M words by 16 bits. This device features
advanced circuit design to provide ultra low active current. This
is ideal for providing More Battery Life™ (MoBL^®) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that reduces power consumption
by 99% when addresses are not toggling. The device can also
be put into standby mode when deselected (CE₁ HIGH or CE₂
LOW or both BHE and BLE are HIGH). The input and output pins
(IO₀ through IO₁₅) are placed in a high impedance state when:
the device is deselected (CE₁HIGH or CE₂ LOW); outputs are
disabled (OE HIGH); both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH); when a write operation
is in progress (CE₁ LOW, CE₂ HIGH and WE LOW).
To write to the device, take Chip Enables (CE₁ LOW and CE₂
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO₀ through IO₇) is written
into the location specified on the address pins (A₀ through A₂₀).
If Byte High Enable (BHE) is LOW, then data from IO pins (IO₈
through IO₁₅) is written into the location specified on the address
pins (A₀ through A₂₀).
To read from the device, take Chip Enables (CE₁ LOW and CE₂
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on IO₀ to IO₇. If Byte High Enable (BHE) is LOW, then data from
memory appears on IO₈ to IO₁₅. See the Truth Table on page 9
for a complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
A₁₀
A₉
A₈
A₇
A₆
A₅
A₄
A₃
A₂
A₁
A₀
DATA IN DRIVERS
2M × 16
RAM ARRAY
IO₀–IO₇
IO₈–IO₁₅
COLUMN DECODER
Power Down
Circuit
CE₂
CE₁
BHE
BLE
BHE
WE
CE₂
OE
CE₁
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-44018 Rev. **
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 08, 2008
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