CY62168EV30_11 Datasheet, PDF (1/16 Pages) Cypress Semiconductor – 16-Mbit (2 M x 8) Static RAM Automatic power-down when deselected

CY62168EV30 MoBL^®
16-Mbit (2 M × 8) Static RAM
16-Mbit (2 M × 8) Static RAM
Features
■ Very high speed: 45 ns
■ Wide voltage range: 2.20 V to 3.60 V
■ Ultra low standby power
❐ Typical standby current: 1.5 µA
❐ Maximum standby current: 12 µA
■ Ultra low active power
❐ Typical active current: 2.2 mA at f = 1 MHz
■ Easy memory expansion with CE₁, CE₂ and OE features
■ Automatic power-down when deselected
■ CMOS for optimum speed/power
■ Offered in Pb-free 48-ball FBGA package. For Pb-free 48-pin
TSOP I package, refer to CY62167EV30 datasheet.
Functional Description
The CY62168EV30 is a high performance CMOS static RAM
organized as 2 M words by 8-bits. This device features advanced
circuit design to provide an ultra low active current. This is ideal
for providing More Battery Life (MoBL^) in portable
applications such as cellular telephones. The device also has an
automatic power-down feature that significantly reduces power
consumption by 90% when addresses are not toggling. Placing
the device into standby mode reduces power consumption by
more than 99% when deselected (Chip Enable 1 (CE₁) HIGH or
Chip Enable 2 (CE₂) LOW). The input and output pins (I/O₀
through I/O₇) are placed in a high impedance state when: the
device is deselected (Chip Enable 1 (CE₁) HIGH or
Chip Enable 2 (CE₂) LOW), outputs are disabled (OE HIGH), or
a write operation is in progress (Chip Enable 1 (CE₁) LOW and
Chip Enable 2 (CE₂) HIGH and WE LOW).
Write to the device by taking Chip Enable 1 (CE₁) LOW and
Chip Enable 2 (CE₂) HIGH and the Write Enable (WE) input
LOW. Data on the eight I/O pins (I/O₀ through I/O₇) is then written
into the location specified on the address pins (A₀ through A₂₀).
Read from the device by taking Chip Enable 1 (CE₁) and
Output Enable (OE) LOW and Chip Enable 2 (CE₂) HIGH while
forcing Write Enable (WE) HIGH. Under these conditions, the
contents of the memory location specified by the address pins
will appear on the I/O pins.
The eight input and output pins (I/O₀ through I/O₇) are placed in
a high impedance state when the device is deselected (CE₁
HIGH or CE₂ LOW), the outputs are disabled (OE HIGH), or a
write operation is in progress (CE₁ LOW and CE₂ HIGH and WE
LOW). See the Truth Table on page 11 for a complete description
of read and write modes.
Logic Block Diagram
CE1
CE2
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
WE
OE
DATA IN DRIVERS
2M x 8
ARRAY
COLUMN DECODER
POWER
DOWN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-07721 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 10, 2011
[+] Feedback