CY62168EV30 Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 16-Mbit (2M x 8) Static RAM

CY62168EV30 MoBL^®
16-Mbit (2M x 8) Static RAM
Features
• Very high speed: 45 ns
• Wide voltage range: 2.20V – 3.60V
• Ultra low standby power
— Typical standby current: 1.5 µA
— Maximum standby current: 12 µA
• Ultra low active power
— Typical active current: 2.2 mA @ f = 1 MHz
• Easy memory expansion with CE₁, CE₂ and OE features
• Automatic power down when deselected
• CMOS for optimum speed/power
• Offered in Pb-free 48-ball FBGA package. For Pb-free
48-pin TSOP I package, refer to CY62167EV30 data sheet.
Functional Description^[1]
The CY62168EV30 is a high performance CMOS static RAM
organized as 2M words by 8 bits. This device features
advanced circuit design to provide an ultra low active current.
This is ideal for providing More Battery Life™ (MoBL^®) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption by 90% when addresses are not
toggling. Placing the device into standby mode reduces power
consumption by more than 99% when deselected (Chip
Enable 1 (CE₁) HIGH or Chip Enable 2 (CE₂) LOW). The input
and output pins (IO₀ through IO₇) are placed in a high
impedance state when: the device is deselected (Chip Enable
1 (CE₁) HIGH or Chip Enable 2 (CE₂) LOW), outputs are
disabled (OE HIGH), or a write operation is in progress (Chip
Enable 1 (CE₁) LOW and Chip Enable 2 (CE₂) HIGH and WE
LOW).
Write to the device by taking Chip Enable 1 (CE₁) LOW and
Chip Enable 2 (CE₂) HIGH and the Write Enable (WE) input
LOW. Data on the eight IO pins (IO₀ through IO₇) is then
written into the location specified on the address pins (A₀
through A₂₀).
Read from the device by taking Chip Enable 1 (CE₁) and
Output Enable (OE) LOW and Chip Enable 2 (CE₂) HIGH
while forcing Write Enable (WE) HIGH. Under these condi-
tions, the contents of the memory location specified by the
address pins will appear on the IO pins.
The eight input and output pins (IO₀ through IO₇) are placed
in a high impedance state when the device is deselected (CE₁
LOW and CE₂ HIGH), the outputs are disabled (OE HIGH), or
a write operation is in progress (CE₁ LOW and CE₂ HIGH and
WE LOW). See the “Truth Table” on page 8 for a complete
description of read and write modes.
Logic Block Diagram
A0
DATA IN DRIVERS
A1
IO0
A2
A3
IO1
A4
A5
IO2
A6
2M x 8
A7
IO3
A8
ARRAY
A9
IO4
A10
A11
IO5
A12
IO6
CE1
CE2
WE
COLUMN DECODER
POWER
DOWN
IO7
OE
Note
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation
Document #: 001-07721 Rev. *B
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised June 07, 2007
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