CY62167E_13 Datasheet, PDF (1/17 Pages) Cypress Semiconductor – 16-Mbit (1 M x 16 / 2 M x 8) Static RAM

CY62167E MoBL^®
16-Mbit (1 M × 16 / 2 M × 8) Static RAM
16-Mbit (1 M × 16 / 2 M × 8) Static RAM
Features
■ Configurable as 1 M × 16 or as 2 M × 8 SRAM
■ Very high speed: 45 ns
■ Wide voltage range: 4.5 V to 5.5 V
■ Ultra low standby power
❐ Typical standby current: 1.5 µA
❐ Maximum standby current: 12 µA
■ Ultra low active power
❐ Typical active current: 2.2 mA at f = 1 MHz
■ Easy memory expansion with CE₁, CE₂, and OE features
■ Automatic power-down when deselected
■ CMOS for optimum speed and power
■ Offered in 48-pin TSOP I package
Functional Description
The CY62167E is a high performance CMOS static RAM
organized as 1 M words by 16-bits/2 M words by 8-bits. This
device features advanced circuit design to provide an ultra low
active current. This is ideal for providing More Battery Life
(MoBL^®) in portable applications. The device also has an
automatic power down feature that reduces power consumption
when addresses are not toggling. Place the device into standby
mode when deselected (CE₁ HIGH, or CE₂ LOW, or both BHE
and BLE are HIGH). The input and output pins (I/O₀ through
I/O₁₅) are placed in a high impedance state when:
■ The device is deselected (CE₁ HIGH or CE₂ LOW)
■ Outputs are disabled (OE HIGH)
■ Both byte high enable and byte low enable are disabled (BHE,
BLE HIGH) or
■ A write operation is in progress (CE₁ LOW, CE₂ HIGH, and WE
LOW)
To write to the device, take chip enables (CE₁ LOW and CE₂
HIGH) and write enable (WE) input LOW. If byte low enable
(BLE) is LOW, then data from I/O pins (I/O₀ through I/O₇), is
written into the location specified on the address pins (A₀ through
A₁₉). If byte high enable (BHE) is LOW, then data from the I/O
pins (I/O₈ through I/O₁₅) is written into the location specified on
the address pins (A₀ through A₁₉).
To read from the device, take chip enables (CE₁ LOW and CE₂
HIGH) and output enable (OE) LOW while forcing the write
enable (WE) HIGH. If byte low enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on I/O₀ to I/O₇. If byte high enable (BHE) is LOW, then data from
memory appears on I/O₈ to I/O₁₅. See Truth Table on page 12
for a complete description of read and write modes.
The CY62167E device is suitable for interfacing with processors
that have TTL I/P levels. It is not suitable for processors that
require CMOS I/P levels. Please see Electrical Characteristics
on page 4 for more details and suggested alternatives.
Logic Block Diagram
A₁₀
A₉
A
A
A
8
7
6
A₅
A₄
A₃
A₂
A
A
1
0
DATA IN DRIVERS
1 M × 16 / 2 M × 8
RAM ARRAY
I/O₀–I/O₇
I/O₈–I/O₁₅
POWER DOWN
CIRCUIT
COLUMN DECODER
CE₂
CE₁
BHE
BLE
BYTE
BHE
WE
CE₂
OE
CE₁
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-15607 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 10, 2013