CY62167EV30_09 Datasheet, PDF (1/14 Pages) Cypress Semiconductor – 16-Mbit (1M x 16 / 2M x 8) Static RAM

CY62167EV30 MoBL^®
16-Mbit (1M x 16 / 2M x 8) Static RAM
Features
■ TSOP I Package Configurable as 1M x 16 or 2M x 8 SRAM
■ Very High Speed: 45 ns
■ Temperature Ranges
❐ Industrial: –40°C to +85°C
❐ Automotive-A: –40°C to +85°C
■ Wide Voltage Range: 2.20V to 3.60V
■ Ultra Low Standby Power
❐ Typical standby current: 1.5 μA
❐ Maximum standby current: 12 μA
■ Ultra Low Active Power
❐ Typical active current: 2.2 mA at f = 1 MHz
■ Easy Memory Expansion with CE₁, CE₂, and OE Features
■ Automatic Power Down when Deselected
■ CMOS for Optimum Speed and Power
■ Offered in Pb-free 48-Ball VFBGA and 48-Pin TSOP I
Packages
Functional Description
The CY62167EV30 is a high performance CMOS static RAM
organized as 1M words by 16 bits or 2M words by 8 bits. This
device features an advanced circuit design that provides an ultra
low active current. Ultra low active current is ideal for providing
More Battery Life™ (MoBL^®) in portable applications such as
cellular telephones. The device also has an automatic power
down feature that reduces power consumption by 99 percent
when addresses are not toggling. Place the device into standby
mode when deselected (CE₁ HIGH or CE₂ LOW or both BHE and
BLE are HIGH). The input and output pins (I/O₀ through I/O₁₅)
are placed in a high impedance state when: the device is
deselected (CE₁ HIGH or CE₂ LOW), outputs are disabled (OE
HIGH), both Byte High Enable and Byte Low Enable are disabled
(BHE, BLE HIGH), or a write operation is in progress (CE₁ LOW,
CE₂ HIGH and WE LOW).
To write to the device, take Chip Enables (CE₁ LOW and CE₂
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O₀ through I/O₇) is
written into the location specified on the address pins (A₀ through
A₁₉). If Byte High Enable (BHE) is LOW, then data from the I/O
pins (I/O₈ through I/O₁₅) is written into the location specified on
the address pins (A₀ through A₁₉).
To read from the device, take Chip Enables (CE₁ LOW and CE₂
HIGH) and Output Enable (OE) LOW while forcing the Write
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data
from the memory location specified by the address pins appears
on I/O₀ to I/O₇. If Byte High Enable (BHE) is LOW, then data from
memory appears on I/O₈ to I/O₁₅. See the “Truth Table” on
page 9 for a complete description of read and write modes.
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
A₁₀
A₉
A₈
A₇
A₆
A₅
A₄
A₃
A₂
A₁
A₀
DATA IN DRIVERS
1M × 16 / 2M x 8
RAM Array
COLUMN DECODER
Power Down
Circuit
CE₂
CE₁
BHE
BLE
IO₀–IO₇
IO₈–IO₁₅
BYTE
BHE
WE
CE₂
OE
CE₁
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-05446 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 17, 2009
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