CY62167EV30 Datasheet, PDF (1/13 Pages) Cypress Semiconductor – 16-Mbit (1M x 16 / 2M x 8) Static RAM

CY62167EV30 MoBL^®
16-Mbit (1M x 16 / 2M x 8) Static RAM
Features
• TSOP I package configurable as 1M x 16 or as 2M x 8 SRAM
• Very high speed: 45 ns
• Wide voltage range: 2.20V–3.60V
• Ultra low standby power
— Typical standby current: 1.5 µA
— Maximum standby current: 12 µA
• Ultra low active power
— Typical active current: 2.2 mA @ f = 1 MHz
• Easy memory expansion with CE₁, CE₂, and OE features
• Automatic power down when deselected
• CMOS for optimum speed/power
• Offered in Pb-free 48-ball BGA and 48-pin TSOP I packages
Functional Description^[1]
The CY62167EV30 is a high performance CMOS static RAM
organized as 1M words by 16 bits / 2M words by 8 bits. This
device features advanced circuit design to provide an ultra low
active current. This is ideal for providing More Battery Life™
(MoBL^®) in portable applications such as cellular telephones.
The device also has an automatic power down feature that
Logic Block Diagram
significantly reduces power consumption by 99% when
addresses are not toggling. Place the device into standby
mode when deselected (CE₁ HIGH or CE₂ LOW or both BHE
and BLE are HIGH). The input and output pins (IO₀ through
IO₁₅) are placed in a high-impedance state when: the device
is deselected (CE₁ HIGH or CE₂ LOW), outputs are disabled
(OE HIGH), both Byte High Enable and Byte Low Enable are
disabled (BHE, BLE HIGH), or a write operation is in progress
(CE₁ LOW, CE₂ HIGH and WE LOW).
To write to the device, take Chip Enables (CE₁ LOW and CE₂
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from IO pins (IO₀ through IO₇) is
written into the location specified on the address pins (A₀
through A₁₉). If Byte High Enable (BHE) is LOW, then data
from the IO pins (IO₈ through IO₁₅) is written into the location
specified on the address pins (A₀ through A₁₉).
To read from the device, take Chip Enables (CE₁ LOW and
CE₂ HIGH) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on IO₀ to IO₇. If Byte High Enable (BHE) is
LOW, then data from memory will appear on IO₈ to IO₁₅. See
the “Truth Table” on page 10 for a complete description of read
and write modes.
Power Down
Circuit
DATA IN DRIVERS
A₁₀
A₉
A₈
A₇
A₆
1M × 16 / 2M x 8
A₅
RAM Array
A₄
A₃
A₂
A
A
1
0
COLUMN DECODER
CE₂
CE₁
BHE
BLE
IO₀–IO₇
IO₈–IO₁₅
BYTE
BHE
WE
CE₂
OE
CE₁
BLE
Note
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation
Document #: 38-05446 Rev. *C
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised June 04, 2007
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