CY62158DV30 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 8-Mbit (1024K x 8) MoBL Static RAM

CY62158DV30
MoBL^
8-Mbit (1024K x 8) MoBL^ Static RAM
Features
• Very high speed: 45 ns, 55 ns and 70 ns
— Wide voltage range: 2.20V – 3.60V
• Ultra-low active power
— Typical active current:1.5 mA @ f = 1 MHz
— Typical active current: 12 mA @ f = f_max
• Ultra-low standby power
• Easy memory expansion with CE₁, CE₂, and OE
features
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Packages offered in a 48-ball BGA, 48-pin TSOPI, and
44-pin TSOPII
Functional Description^[1]
The CY62158DV30 is a high-performance CMOS static RAMs
organized as 1024K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
Logic Block Diagram
This is ideal for providing More Battery Life™ (MoBL^) in
portable applications such as cellular telephones. The device
also has an automatic power-down feature that significantly
reduces power consumption. The device can be put into
standby mode reducing power consumption by 85% when
deselected (CE₁ HIGH or CE₂ LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE₁) and Write Enable (WE) inputs LOW and Chip Enable 2
(CE₂) HIGH. Data on the eight I/O pins (I/O₀ through I/O₇) is
then written into the location specified on the address pins (A₀
through A₁₉).
Reading from the device is accomplished by taking Chip
Enable 1 (CE₁) and Output Enable (OE) LOW and Chip
Enable 2 (CE₂) HIGH while forcing Write Enable (WE) HIGH.
Under these conditions, the contents of the memory location
specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O₀ through I/O₇) are placed in a
high-impedance state when the device is deselected (CE₁
LOW and CE₂ HIGH), the outputs are disabled (OE HIGH), or
during a write operation (CE₁ LOW and CE₂ HIGH and WE
LOW). See the truth table for a complete description of read
and write modes.
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Data in Drivers
1024K x 8
ARRAY
CE₁
CE₂
WE
OE
COLUMN
DECODER
POWER
DOWN
I/O₀
I/O₁
I/O₂
I/O₃
I/O₄
I/O₅
I/O₆
I/O₇
Note:
1. For best practice recommendations, please refer to the Cypress application note entitled System Design Guidelines, available at http://www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05391 Rev. *D
Revised June 17, 2004
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